Digital LogicUnit 29 min read
Boolean Algebra & Logic Gates: Laws, Gates, Truth Tables & Simplification
Unit 2 of Digital Logic covers Boolean algebra’s laws and postulates, logic gate symbols and truth tables, gate combinations for AND/OR/NOT/XOR/XNOR, and simplification using algebraic laws and Karnaugh Maps (K-Maps). Real-world applications in eSewa’s transaction logic, Ncell’s call routing, and Daraz’s order prioriti
TAKEAWAYS:
- Boolean algebra uses 1 (true) and 0 (false) with AND (·), OR (+), and NOT (′) operations, unlike binary arithmetic which adds/subtracts.
- Logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) implement Boolean functions physically; their symbols and truth tables are examinable.
- Simplification reduces circuits using Boolean laws (De Morgan’s, distributive, absorption) or K-Maps (grouping adjacent 1s in 2^n cells).
- Universal gates: NAND and NOR alone can build any logic function (proof via De Morgan’s).
- Real-world tie: eSewa’s transaction approval uses XOR to detect duplicate payments; Ncell’s call routing uses MUX-like selection.
- Exam focus: Truth tables, gate combinations, and K-Map groupings (3- or 4-variable) appear in 60% of questions.
1. Boolean Algebra: Foundations
Boolean algebra is a mathematical system for manipulating binary variables (0/1) using logical operations. Unlike arithmetic, it follows truth-based rules (e.g., in OR logic).
Key Postulates and Laws
| Law | Expression | Explanation |
|---|---|---|
| Identity | , | 0/1 act as additive/multiplicative identities. |
| Complement | , | (NOT A) flips the value. |
| Idempotent | , | Repeating a variable doesn’t change the result. |
| Commutative | , | Order doesn’t matter. |
| Associative | Grouping doesn’t affect the result. | |
| Distributive | Like arithmetic distribution. | |
| Absorption | Reduces redundant terms. | |
| De Morgan’s | , | Converts AND/OR to OR/AND via NOTs. |
Worked Example: Simplify
- Factor from the first and third terms: .
- Since , simplify to: . Result: The expression is already simplified (no further reductions possible).
2. Logic Gates: Symbols and Truth Tables
Logic gates are physical implementations of Boolean operations. Below are their standard symbols (IEC 60617) and truth tables.
Basic Gates
| Gate | Symbol | Truth Table | Boolean Expression |
|---|---|---|---|
| AND | `A -- | > | -- B` |
| OR | `A -- | /-- B` | |
| NOT | A --o--> |
Output inverts input. | |
| NAND | `A -- | > | -- B` with small circle |
| NOR | `A -- | /-- B` with small circle | |
| XOR | A --⊕-- B |
Output = 1 if inputs differ. | |
| XNOR | A --≡-- B |
Output = 1 if inputs are equal. |
Universal Gates: NAND and NOR
- NAND and NOR are universal because they can implement all other gates using De Morgan’s laws.
- Example: Build a NOT gate using NAND: Connect both inputs of a NAND gate together → output = .
NAND-only NOT, AND, OR circuits (Image: Topeil, CC0, via Wikimedia Commons)
3. Gate Combinations and Real-World Logic
Half Adder and Full Adder
A half adder adds two bits; a full adder adds three bits (including a carry-in).
Half Adder Truth Table:
| A | B | Sum (S) | Carry (C) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Boolean Expressions:
- Sum:
- Carry:
Full Adder Logic Diagram:
Real-World Tie: Daraz Order Processing Daraz’s order prioritization system uses a priority encoder (a combinational circuit) to route high-value orders faster. The logic resembles a full adder’s carry propagation to determine urgency levels.
4. Simplification Techniques
Algebraic Simplification
Use Boolean laws to reduce expressions before implementation. Example: Simplify .
- Factor from the first and third terms: .
- Apply absorption: (since absorbs ).
Karnaugh Maps (K-Maps)
K-Maps visually group adjacent 1s to simplify expressions. They work for 2–4 variables.
3-Variable K-Map Example: Simplify .
AB\C | 0 1
-----|----
00 | 1 1
01 | 1 0
11 | 1 1
10 | 0 -
Groups:
- Group 1: Cells 0,1 (row 00) →
- Group 2: Cells 2,3,6,7 (column 1) →
- Group 3: Cells 5,7 (diagonal) →
Simplified Expression: .
4-Variable K-Map Example
Simplify .
BC\AD | 00 01 11 10
---------------------
00 | 1 0 0 1
01 | 0 1 1 0
11 | 1 1 - -
10 | 0 0 - -
Groups:
- Group 1: Cells 0,1,8,9 →
- Group 2: Cells 2,3,10,11 →
- Group 3: Cells 12,13,14,15 →
Simplified Expression: (further simplified).
5. Applications in Nepal’s Tech Industry
| Company/Product | Boolean Logic Used | How It Works |
|---|---|---|
| eSewa | XOR gates for duplicate detection | XOR compares transaction IDs; output = 1 if IDs differ (fraud alert). |
| Ncell Prepaid | MUX for call routing | 4:1 MUX selects between voice, SMS, or data based on input signals. |
| Daraz Orders | Priority encoder for order sorting | Encodes order IDs into binary; higher bits = higher priority. |
| NTC Traffic Lights | Timer-based sequential circuits | Uses flip-flops to cycle through red/yellow/green states. |
| Khalti Payments | AND gates for double authentication | Both OTP and PIN must be correct (AND) to approve payment. |
Worked Example: Ncell’s Call Routing A 4:1 MUX selects between:
- Voice (S0=00)
- SMS (S0=01)
- Data (S0=10)
- Emergency (S0=11)
Truth Table:
| S1 | S0 | Output (Y) |
|---|---|---|
| 0 | 0 | Voice |
| 0 | 1 | SMS |
| 1 | 0 | Data |
| 1 | 1 | Emergency |
Boolean Expression: .
6. Exam Tip: What to Focus On
- Truth Tables: Always draw them for gate combinations (e.g., half/full adders).
- K-Maps: Practice 3- and 4-variable maps; grouping rules:
- Groups must be powers of 2 (1, 2, 4, 8).
- Wrap around edges (e.g., 0 and 4 in a 4-variable map).
- Universal Gates: Prove NAND/NOR can build NOT, AND, OR.
- Real-World Links: Relate adders to bank loan interest calculations (binary addition) or traffic light timers (sequential logic).
- Shortcuts:
- Memorize De Morgan’s for gate conversions.
- For K-Maps, start with the largest possible group.
Common Pitfalls:
- Forgetting to invert in De Morgan’s (e.g., ).
- Misgrouping in K-Maps (e.g., grouping 1s diagonally when they’re not adjacent).
- Missing terms in truth tables (always list all combinations).
Based on the TU BCA syllabus for Digital Logic (CACS103), unit 2.
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