Microprocessor and Computer ArchitectureUnit 714 min read
Data Transfer & Manipulation Instructions: 8085 Operations, Formats & Real-World Use
Unit 7 of Microprocessor and Computer Architecture explores the 8085 microprocessor’s data transfer and manipulation instructions, their formats, addressing modes, and practical applications in embedded systems and assembly programming. This note covers instruction classification, execution traces, and real-world examp
TAKEAWAYS:
- 8085 instructions are classified into 5 groups: data transfer, arithmetic, logic, branch, and stack/IO—with data transfer being the most fundamental for moving data between registers, memory, and I/O ports.
- Instruction formats define how operands are encoded (e.g.,
MOV A,Bvs.MVI A,32H), with 3-byte formats used for complex operations likeLXI H,addr. - Addressing modes determine how operands are specified (e.g., immediate, register, direct, register indirect), directly impacting instruction length and execution speed.
- Worked examples (e.g., loading a value to
A, adding two memory locations) show how to trace register/memory changes step-by-step using the instruction cycle and T-states. - Real-world ties: WhatsApp uses data transfer instructions to move encrypted messages between buffers; Ncell’s billing system relies on memory-to-register transfers for processing SIM data.
- Exam focus: Expect programming questions (e.g., "Write a program to swap two memory locations") and trace questions (e.g., "Show the register states after
LDA 2050H; ADD B").
1. Classification of 8085 Instructions
The 8085 instruction set is divided into 5 categories, but this unit focuses on data transfer and arithmetic/logic manipulation instructions. These are the building blocks for all programs.
classDiagram
class InstructionSet {
+Data Transfer (e.g., MOV, MVI, LDA, STA)
+Arithmetic (e.g., ADD, SUB, INC, DCR)
+Logic (e.g., ANA, XRA, CMP)
+Branch (e.g., JMP, CALL, RET)
+Stack/IO (e.g., PUSH, POP, IN, OUT)
}
InstructionSet --> DataTransfer : Focus Area
InstructionSet --> Arithmetic : Focus Area
InstructionSet --> Logic : Focus AreaKey Subtopics:
- Data Transfer Instructions: Move data between registers, memory, and I/O ports.
- Arithmetic Instructions: Perform operations like
ADD,SUB,INC,DCR. - Logic Instructions: Bitwise operations (
ANA=AND,XRA=XOR,ORA=OR). - Implied vs. Explicit Operands: Some instructions (e.g.,
INR B) use implied operands, while others (e.g.,ADD M) require explicit addressing.
2. Data Transfer Instructions: Syntax, Formats, and Examples
Data transfer instructions move data between:
- Registers (e.g.,
MOV B,C), - Registers and memory (e.g.,
STA 2050H), - Immediate values and registers/memory (e.g.,
MVI A,32H).
A. Instruction Formats
The 8085 uses 3 formats for data transfer instructions:
| Format | Opcode | Operand | Example | Bytes | T-states |
|---|---|---|---|---|---|
| 1-byte | 1 | None (implied) | MOV B,A |
1 | 4 |
| 2-byte | 1 | 1 byte (8-bit) | MVI A,32H |
2 | 7 |
| 3-byte | 1 | 2 bytes (16-bit) | LXI H,2050H |
3 | 10 |
Visual: 8085 Instruction Format Breakdown
B. Common Data Transfer Instructions
| Instruction | Mnemonic | Operation | Example | Bytes | T-states |
|---|---|---|---|---|---|
| Move | MOV dest,src |
Copy src to dest (register/register or register/memory) |
MOV B,C |
1 | 4 |
| Move Immediate | MVI dest,data8 |
Load data8 into dest (register or memory) |
MVI A,0FFH |
2 | 7 |
| Load Accumulator | LDA addr16 |
Load memory addr16 into A |
LDA 2050H |
3 | 13 |
| Store Accumulator | STA addr16 |
Store A into memory addr16 |
STA 2051H |
3 | 13 |
| Load HL Pair | LXI H,addr16 |
Load 16-bit addr16 into HL register pair |
LXI H,2050H |
3 | 10 |
| Move Memory | MOV M,src |
Move src (register) to memory [HL] |
MOV M,B |
1 | 7 |
3. Addressing Modes in Data Transfer
Addressing modes determine how the operand is specified. For data transfer, the key modes are:
| Mode | Description | Example | Bytes | T-states |
|---|---|---|---|---|
| Immediate | Operand is part of the instruction. | MVI A,32H |
2 | 7 |
| Register | Operand is a register (e.g., B, C). |
MOV B,A |
1 | 4 |
| Direct | Operand is a memory address (8-bit). | STA 50H (if using M notation) |
2 | 10 |
| Register Indirect | Operand is memory [HL] or [BC]. |
MOV M,A (store A to [HL]) |
1 | 7 |
| 16-bit Address | Operand is a 16-bit memory address. | LDA 2050H |
3 | 13 |
Real-World Analogy:
- Immediate mode is like pre-filling a form (e.g.,
MVI A,5loads5directly intoA). - Register indirect is like using a pointer (e.g.,
MOV M,BstoresBto the address inHL).
4. Worked Example: Loading and Adding Two Memory Values
Problem: Write a program to add two numbers stored at 2050H and 2051H, and store the result at 2052H.
Solution:
LXI H,2050H ; Load HL with starting address (2050H)
MOV A,M ; Load [HL] (2050H) into A
INX H ; Increment HL to point to 2051H
ADD M ; Add [HL] (2051H) to A
STA 2052H ; Store result at 2052H
HLT ; Halt
Step-by-Step Trace:
| Instruction | Operation | Register/Memory State | T-states |
|---|---|---|---|
LXI H,2050H |
Load HL with 2050H |
HL = 2050H, A = ?, [2050H] = ?, [2051H] = ? |
10 |
MOV A,M |
A = [HL] ([2050H] into A) |
A = [2050H], HL = 2050H |
7 |
INX H |
HL = HL + 1 (2050H → 2051H) |
HL = 2051H |
5 |
ADD M |
A = A + [HL] (A + [2051H]) |
A = [2050H] + [2051H], HL = 2051H |
7 |
STA 2052H |
Store A to 2052H |
[2052H] = [2050H] + [2051H] |
13 |
Real-World Tie: This is how Ncell’s billing system calculates total call charges by adding individual call durations stored in memory locations.
5. Arithmetic and Logic Manipulation Instructions
These instructions modify data in registers or memory.
A. Arithmetic Instructions
| Instruction | Operation | Flags Affected | Example |
|---|---|---|---|
ADD src |
A = A + src |
Z,S,C,AC,P | ADD B |
SUB src |
A = A - src |
Z,S,C,AC,P | SUB M |
INR src |
Increment src by 1 |
Z,S,P | INR C |
DCR src |
Decrement src by 1 |
Z,S,P | DCR D |
INX src |
Increment 16-bit register pair (BC, DE, HL, SP) |
None | INX H |
DCX src |
Decrement 16-bit register pair | None | DCX SP |
Example: Calculate A = A + B + C and store in A.
MOV A,B ; A = B
ADD C ; A = A + C
B. Logic Instructions
| Instruction | Operation | Flags Affected | Example |
|---|---|---|---|
ANA src |
A = A AND src |
Z,S,P | ANA B |
XRA src |
A = A XOR src |
Z,S,P | XRA M |
ORA src |
A = A OR src |
Z,S,P | ORA C |
CMP src |
A - src (sets flags for comparison) |
Z,S,C,AC,P | CMP B |
Example: Clear the least significant bit (LSB) of A.
ANI 0FEH ; AND with 0FEH (binary: 11111110) clears LSB
6. Stack Operations (Bonus: Relevant to Data Transfer)
The stack is used for subroutine calls, interrupts, and temporary storage. Key instructions:
PUSH psw: PushesAand flags onto the stack.POP psw: PopsAand flags from the stack.PUSH H: PushesHLpair onto the stack.POP H: PopsHLpair from the stack.
Example: Save HL and A to the stack, then restore.
PUSH H ; Save HL
PUSH PSW ; Save A and flags
; ... (code that modifies HL/A)
POP PSW ; Restore A and flags
POP H ; Restore HL
Real-World Tie:
- eSewa’s payment gateway uses the stack to temporarily store transaction data during processing.
- WhatsApp’s encryption relies on stack operations to manage session keys during message exchanges.
7. Instruction Cycle and T-States Recap
Every instruction follows the instruction cycle, which consists of:
- Fetch: Get opcode from memory.
- Decode: Determine operation.
- Execute: Perform the operation.
Each step takes T-states (clock cycles). For example:
MOV B,Atakes 4 T-states (1 fetch, 3 execute).LDA 2050Htakes 13 T-states (3 fetch, 10 execute).
Visual: Instruction Cycle for MVI A,32H
sequenceDiagram
participant CPU
participant Memory
CPU->>Memory: Fetch Opcode (MVI = 06H)
Memory-->>CPU: Return 06H
CPU->>Memory: Fetch Operand (32H)
Memory-->>CPU: Return 32H
CPU->>CPU: Decode: Move immediate to A
CPU->>CPU: Execute: A = 32H
Note over CPU: Total T-states: 78. Common Exam Questions and Solutions
Q1: Write a program to swap the contents of two memory locations 2050H and 2051H.
Solution:
LXI H,2050H ; Load HL with 2050H
MOV A,M ; A = [2050H]
INX H ; HL = 2051H
MOV B,M ; B = [2051H]
DCX H ; HL = 2050H
MOV M,B ; [2050H] = B (original [2051H])
INX H ; HL = 2051H
MOV M,A ; [2051H] = A (original [2050H])
HLT
Q2: Explain the execution of ADD B with a timing diagram.
Answer:
- Fetch Opcode (
ADD=80H):PCpoints toADD B(assume at2000H).M[2000H] = 80H(opcode forADD B).- T-states: 4 (fetch cycle).
- Decode and Execute:
A = A + B.- Flags (
Z,S,C,AC,P) updated. - T-states: 4 (execute cycle).
- Total T-states: 8.
Timing Diagram:
9. Real-World Applications
A. eSewa’s Transaction Processing
- Data Transfer: When you pay a bill, eSewa moves transaction amounts from memory buffers to the accumulator (
A) for processing. - Arithmetic: Adds taxes to the base amount using
ADDinstructions. - Stack: Temporarily stores user details during verification.
B. Ncell’s Billing System
- Memory Operations: Loads call durations from memory (
LDA addr) and adds them (ADD) to compute total charges. - Logic Operations: Uses
CMPto check if a call exceeds the data limit.
C. WhatsApp’s Encryption (Simplified)
- Register Manipulation: Shifts and XORs data between registers (
XRA,RLC) to encrypt messages. - Immediate Values: Uses
MVIto load encryption keys.
D. Daraz’s Order Queue
- Stack Operations: Manages pending orders using
PUSH/POPto prioritize deliveries.
10. Exam Tip: How to Score Full Marks
For Programming Questions:
- Always comment each step.
- Show register/memory changes in a table (like the worked example above).
- Use pseudo-code if unsure of exact instructions.
For Trace Questions:
- Break down the instruction into fetch, decode, execute.
- Show T-states and flag changes.
- Example: For
ADD B, write:Step 1: Fetch opcode (ADD = 80H) [4 T-states] Step 2: Decode: A = A + B [4 T-states] Flags: Z=?, S=?, C=?, AC=?, P=?
For Theory Questions:
- Compare data transfer vs. arithmetic instructions in a table.
- Explain addressing modes with real examples (e.g., "Immediate mode is used in
MVI A,5to load5directly").
Avoid Common Mistakes:
- Don’t forget flag updates (e.g.,
ADDaffectsZ,S,C). - For 16-bit operations (e.g.,
LXI H), always use 3 bytes. - HLT is not always needed but is safe to include.
- Don’t forget flag updates (e.g.,
11. Summary Table: Key Instructions
| Category | Instruction | Format | Example | T-states | Key Use Case |
|---|---|---|---|---|---|
| Data Transfer | MOV |
1-byte | MOV B,A |
4 | Copy register to register |
MVI |
2-byte | MVI A,32H |
7 | Load immediate value | |
LDA/STA |
3-byte | LDA 2050H |
13 | Load/store accumulator to/from memory | |
| Arithmetic | ADD |
1-byte | ADD B |
4 | Add to accumulator |
INR |
1-byte | INR C |
5 | Increment register | |
| Logic | ANA |
1-byte | ANA B |
4 | Bitwise AND |
| Stack | PUSH/POP |
1-byte | PUSH PSW |
11/10 | Save/restore registers |
Based on the TU BCA syllabus for Microprocessor and Computer Architecture (CACS155), unit 7.
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