Instruction Formats & Assembly: 8085 Assembly, Mnemonics, Operands & Pipeline

TAKEAWAYS:

• Assembly language translates human-readable mnemonics (e.g., MOV, ADD) into binary machine code (e.g., 78h for MOV A,B).
• Instruction formats define how opcodes and operands are structured (1-byte, 2-byte, 3-byte) in 8085.
• Addressing modes determine how operands are specified (immediate, direct, register, etc.), affecting instruction length and execution time.
• Pipelining overlaps instruction fetch, decode, execute, and write-back stages to improve CPU throughput (e.g., 4-segment pipeline in 8085).
• Real-world use: Assembly is critical in embedded systems (e.g., NTC’s smart meters), bootloaders (e.g., BIOS), and performance-critical apps (e.g., Pathao’s ride-matching algorithms).
• Exam focus: Trace instruction execution (e.g., MVI A,32H), compare instruction formats, and explain pipelining stages with timing diagrams.

1. Instruction Formats in 8085

The 8085 microprocessor uses three primary instruction formats to encode operations, operands, and addresses. Each format determines the length of the instruction (1-byte, 2-byte, or 3-byte) and how operands are specified.

1.1 Types of Instruction Formats

classDiagram
    class InstructionFormat {
        +name: String
        +length: Int
        +fields: String[]
    }
    class OneByteFormat {
        +opcode: 8 bits
    }
    class TwoByteFormat {
        +opcode: 8 bits
        +operand: 8 bits
    }
    class ThreeByteFormat {
        +opcode: 8 bits
        +address: 16 bits
    }
    InstructionFormat <|-- OneByteFormat
    InstructionFormat <|-- TwoByteFormat
    InstructionFormat <|-- ThreeByteFormat

1.2 How Instructions Are Encoded

• Opcode: The first byte (or part of it) specifies the operation (e.g., MOV, ADD, JMP).
• Operand: Additional bytes specify data, addresses, or registers.
  • Immediate data: Directly embedded in the instruction (e.g., MVI A,32H loads 32H into A).
  • Memory address: 16-bit address for memory operations (e.g., STA 3000H stores A to 3000H).
  • Register: 3-bit code for registers (e.g., B = 000, C = 001).

2. Assembly Language Programming

Assembly language is a low-level programming language where each instruction corresponds to a machine code opcode. It uses mnemonics (e.g., MOV, JMP) and symbolic addresses (e.g., START, LOOP) for readability.

2.1 Mnemonics and Operands

• Mnemonic: Shortcode for an operation (e.g., ADD for addition).
• Operand: Specifies the source/destination (register, memory, or immediate value).
  • Example: ADD B (add register B to A).
  • Example: ADD M (add memory location pointed to by HL to A).

2.2 Example: Adding Two Numbers

Problem: Add two numbers stored in memory locations 3000H and 3001H, store the result in 3002H. Solution:

LXI H,3000H   ; Load HL with address 3000H
MOV A,M       ; Load A with data at [HL] (first number)
INX H         ; Increment HL to point to 3001H
ADD M         ; Add data at [HL] (second number) to A
STA 3002H     ; Store result in 3002H
HLT           ; Halt the processor

Binary Execution Trace:

3. Addressing Modes in 8085

Addressing modes define how the operand is specified in an instruction. The 8085 supports 6 primary addressing modes:

mindmap
  root((Addressing Modes in 8085))
    Immediate
    Register
    Direct
    Register Indirect
    Implied
    Jump/Calls

Real-World Example:

• NTC Smart Meters: Use direct addressing to read energy consumption data from specific memory locations in the meter’s microcontroller.
• Pathao Ride Matching: Uses register indirect addressing to dynamically access driver/ride data stored in arrays (e.g., HL points to the next available ride request).

4. Instruction Pipeline in 8085

Pipelining is a technique to overlap instruction execution to improve throughput. The 8085 uses a 4-segment pipeline:

stateDiagram-v2
    [*] --> Fetch: Opcode Fetch
    Fetch --> Decode: Instruction Decode
    Decode --> Execute: Execute ALU/Control
    Execute --> Writeback: Write Result
    Writeback --> [*]

4.1 Pipeline Stages

Example: Execute ADD B (opcode 80h).

1. T1-T2: Fetch 80h from memory.
2. T3: Decode 80h → ADD B (add B to A).
3. T4: Execute A = A + B in ALU.
4. T5: Write result back to A.

Advantages of Pipelining:

• Higher throughput: Multiple instructions in different stages at once.
• Reduced idle time: Overlaps fetch/decode/execute/writeback.

Disadvantages:

• Pipeline hazards: Stalls if data is not ready (e.g., ADD waiting for MOV to complete).
• Complex control logic: Requires careful timing and synchronization.

5. RISC vs. CISC: Instruction Format Comparison

While 8085 is a CISC (Complex Instruction Set Computer), modern CPUs like ARM (RISC) differ in instruction design.

Real-World Tie-In:

• Khalti Payments: Uses RISC-based ARM processors in payment terminals for faster transaction processing (fixed-length instructions reduce decoding time).
• Nepal Rastra Bank’s Core Banking: Relies on CISC architectures for legacy system compatibility (e.g., complex financial calculations in a single instruction).

6. Worked Example: Tracing MVI A,32H Execution

Instruction: MVI A,32H (Move Immediate to Accumulator). Binary: 3Eh 32h (2-byte format).

Step-by-Step Execution:

1. Fetch Opcode (T1-T2):

   • PC holds 3000H (assume instruction starts here).
   • Fetch 3Eh (opcode for MVI) from 3000H.
   • Increment PC to 3001H.

2. Fetch Operand (T3-T4):

   • Fetch 32h (immediate data) from 3001H.
   • Increment PC to 3002H.

3. Execute (T5-T6):

   • Decode MVI A,32h → Load 32h into A.
   • Update A register to 32h.

4. Writeback (T7):

   • No explicit writeback (result is in A).

Timing Diagram:

Real-World Link:

• Ncell’s USSD Menu System: Uses MVI instructions to load menu options into registers for quick display (e.g., MVI A,01H to show "Balance Inquiry").

In the Real World

1. eSewa’s Payment Processing:

   • Uses assembly-level optimizations (e.g., MVI for loading transaction IDs) in embedded systems to minimize latency during payment verification.
   • Why? Immediate addressing (MVI) is faster than memory access for critical data like transaction amounts.

2. Pathao’s Ride-Matching Algorithm:

   • Employs register indirect addressing (ADD M, MOV M,A) to dynamically update driver/ride statuses in real-time.
   • Example: LXI H,2000H loads the address of the next ride request, then MOV A,M fetches the request ID.

3. NTC’s Smart Grid Monitoring:

   • Pipelining is used in microcontrollers to overlap:
     • Fetching sensor data (e.g., voltage readings).
     • Decoding commands (e.g., ADD for totalizing consumption).
     • Writing results to memory for billing.
   • Result: Faster response times for grid adjustments.

Exam Tip

1. Instruction Execution Questions:

   • Always trace T-states (e.g., MVI A,32H takes 7 T-states: 2 for opcode fetch, 2 for operand fetch, 3 for execution).
   • Draw timing diagrams for multi-cycle instructions (e.g., STA 3000H).

2. Assembly Programming:

   • For data manipulation (e.g., adding two tables), use:
     • LXI H,start_address to load the base address.
     • MOV A,M / ADD M for element-wise operations.
     • INX H to move to the next element.
   • Example: Adding two 10-byte arrays at 3000H and 3010H, storing results at 3020H:

     LXI H,3000H   ; Point to first array
     LXI D,3010H   ; DE = second array
     LXI B,3020H   ; BC = result array
     MVI C,0Ah     ; Counter = 10
     LOOP: MOV A,M   ; Load from first array
            ADD M     ; Add corresponding element from second array
            STAX B    ; Store result
            INX H     ; Move to next element in first array
            INX D     ; Move to next in second array
            INX H     ; BC already points to result
            DCR C     ; Decrement counter
            JNZ LOOP  ; Repeat until C=0
     

3. Pipelining:

   • Explain stalls (e.g., data hazard if ADD B follows MOV B,C without a wait state).
   • Compare 8085’s 4-stage pipeline with modern RISC pipelines (e.g., ARM’s 15+ stages).

4. Addressing Modes:

   • Direct vs. Indirect: Direct (STA 3000H) is slower (3-byte) than indirect (STAX B for BC-indirect).
   • Immediate vs. Register: MVI A,32H (2-byte) is faster than MOV A,B (1-byte) if B isn’t preloaded.

5. Common Pitfalls:

   • Forgetting to increment PC after multi-byte instructions (e.g., LXI H,2000H skips 2 bytes).
   • Misusing HL in indirect addressing (e.g., ADD M uses HL, not BC or DE).
   • Overlooking carry flags in arithmetic operations (e.g., DAA after ADD).