Flip-Flops, Latches & Memory Basics: SR, D, JK, T, Edge/Level Triggering

Core Concepts

What Are Flip-Flops and Latches?

Flip-flops and latches are sequential logic circuits that store binary data (0 or 1) and change state based on inputs and clock signals. Unlike combinational circuits (which depend only on current inputs), they remember past inputs, making them essential for memory, registers, and counters.

Key Differences:

classDiagram
    class FlipFlop {
        +Triggered by clock edge (rising/falling)
        +State changes only at clock edge
        +Used in registers, counters
    }
    class Latch {
        +Triggered by level (high/low)
        +State changes immediately when input changes
        +Used in temporary storage, data holding
    }
    FlipFlop <|-- Latch : Inherits

Types of Latches

Latches are level-triggered (state changes when input is active, not tied to a clock edge). The two primary types are:

1. SR (Set-Reset) Latch

• Inputs: S (Set), R (Reset)
• Behavior:
  • If S=1, R=0: Output Q=1 (set)
  • If S=0, R=1: Output Q=0 (reset)
  • If S=R=1: Forbidden state (output undefined)
  • If S=R=0: Holds previous state (memory)
• Truth Table:

  S	R	Q (next)	Q̅ (next)
  0	0	Q₀	Q̅₀
  0	1	0	1
  1	0	1	0
  1	1	X	X

2. D (Data/Delay) Latch

• Input: D (Data)
• Behavior: Output Q follows D when Enable=1; otherwise, holds previous state.
• Truth Table:

  Enable	D	Q (next)
  0	X	Q₀
  1	0	0
  1	1	1

Advantages:

• Simpler than SR latch (no forbidden state).
• Used in data holding (e.g., temporary storage in processors).

Disadvantages:

• Asynchronous: State changes immediately with input, causing glitches in high-speed circuits.

Flip-Flops: Clock-Triggered Memory

Flip-flops are edge-triggered (state changes only at clock edges), making them ideal for synchronous circuits.

1. SR Flip-Flop

• Triggering: Rising/falling edge of clock (CLK).
• Inputs: S (Set), R (Reset), CLK.
• Behavior:
  • Changes state only at clock edge (unlike latches).
  • Forbidden state: S=R=1 (use JK flip-flop instead).

Excitation Table (for SR flip-flop):

2. D Flip-Flop

• Input: D (Data), CLK.
• Behavior: Q follows D only at clock edge; otherwise, holds previous state.
• Truth Table:

  CLK	D	Q (next)
  ↑	0	0
  ↑	1	1
  X	X	Q₀

Applications:

• Registers: Store data temporarily (e.g., CPU instruction registers).
• Shift registers: Sequential data transfer (e.g., serial communication).

3. JK Flip-Flop

• Inputs: J, K, CLK.
• Behavior:
  • If J=K=1: Toggles (Q changes state at each clock edge).
  • If J=1, K=0: Sets Q=1.
  • If J=0, K=1: Resets Q=0.
  • If J=K=0: Holds previous state.
• Excitation Table:

  Q₀	Q₁	J	K
  0	0	0	X
  0	1	1	X
  1	0	X	1
  1	1	X	0

Advantages:

• No forbidden state (unlike SR flip-flop).
• Used in counters, registers, and memory.

4. T Flip-Flop (Toggle)

• Input: T (Toggle), CLK.
• Behavior: Q toggles (0→1 or 1→0) at each clock edge if T=1; holds if T=0.
• Truth Table:

  T	Q (next)
  0	Q₀
  1	Q̅₀

Applications:

• Counters: Simple toggle-based counting (e.g., binary counters).
• Divide-by-2 circuits: Used in frequency dividers.

Triggering Mechanisms

Flip-flops can be triggered by level (like latches) or edge (rising/falling). Edge-triggered flip-flops are preferred in modern designs to avoid race conditions.

flowchart LR
    A["Level-Triggered (Latch)"] -->|"State changes immediately"| B["Glitches possible"]
    C["Edge-Triggered (Flip-Flop)"] -->|"State changes at clock edge"| D["Synchronous, no glitches"]

Real-World Example:

• Pathao’s Ride Allocation System: Pathao uses edge-triggered flip-flops in its backend servers to manage ride requests sequentially. When a user requests a ride, the system’s clocked flip-flops ensure that each request is processed in order (no overlapping or lost data), similar to how a D flip-flop stores the request until the driver is assigned.

Flip-Flop Conversions

Flip-flops can be converted from one type to another using logic gates. For example:

• SR → D: Add an inverter to connect S and R to D.
• JK → T: Tie J and K together to T.
• D → T: Use an XOR gate to toggle Q.

Example: Convert JK to T Flip-Flop

   JK Flip-Flop
     J ----┬----
     K ----┴---- T (J=K)
     CLK ----┬----
             │
             ▼
     T Flip-Flop

Applications in Real Systems

1. Khalti’s Transaction Processing

Khalti uses flip-flops in its payment servers to ensure that each transaction is atomically processed (either fully completed or rolled back). A D flip-flop stores the transaction status (pending/completed) until the next clock cycle (e.g., confirmation from the bank), preventing data loss.

2. NTC’s Call Routing System

The Nepal Telecommunications Company (NTC) uses JK flip-flops in its call switching circuits to manage call connections. When a call is routed, the flip-flop toggles between "idle" and "connected" states, ensuring no two calls interfere.

3. Daraz’s Order Queue System

Daraz’s order processing system uses shift registers (made of D flip-flops) to sequentially process orders. Each order is loaded into a flip-flop at a clock pulse, ensuring FIFO (First-In-First-Out) order fulfillment.

Worked Example: Design a Counter Using T Flip-Flops

Problem: Design a 3-bit binary up-counter using T flip-flops.

Solution:

1. T Flip-Flop Toggle Rule: Each flip-flop toggles when its input T=1.
2. Cascade Connection:
   • FF0 toggles every clock cycle (T₀=1).
   • FF1 toggles when FF0 overflows (T₁ = Q₀).
   • FF2 toggles when FF1 overflows (T₂ = Q₁).
3. Circuit:

   CLK ----┬---- FF0 (T=1)
           │
           ▼
   FF0 Q₀ ---┬---- FF1 (T=Q₀)
   FF1 Q₁ ---┬---- FF2 (T=Q₁)
   FF2 Q₂
   

4. State Transition:

   CLK	Q₂	Q₁	Q₀
   0	0	0	0
   1	0	0	1
   2	0	1	0
   3	0	1	1
   4	1	0	0

Exam Tip

1. Memorize Truth Tables: Know the SR, D, JK, and T flip-flop truth tables and excitation tables by heart. Examiners often ask for state transitions or input combinations.
2. Clock Edge vs. Level: Always specify whether a flip-flop is edge-triggered or level-sensitive (latches). This is a common point of confusion.
3. Forbidden States: Avoid S=R=1 in SR flip-flops and J=K=1 in JK flip-flops unless specified.
4. Conversions: Be able to convert between flip-flop types (e.g., SR to D, JK to T) using logic gates.
5. Applications: Relate flip-flops to real-world systems (e.g., counters in traffic lights, registers in CPUs). Questions may ask for practical uses of flip-flops.
6. Timing Diagrams: Practice drawing timing diagrams for flip-flops, showing how outputs change with clock pulses and inputs.

Final Note: Flip-flops and latches are the backbone of digital memory and sequencing. Mastering their behavior, types, and applications will not only help you ace exams but also understand how modern digital systems (from smartphones to banking servers) store and process data reliably.