Arithmetic Circuits & Complements: Adders, Subtractors & Binary Arithmetic

Key Concepts

1. Binary Arithmetic Basics

Binary arithmetic follows these rules (visualized in truth tables and circuit diagrams):

Why it matters:

• Computers use 2’s complement for all arithmetic (even addition!) to simplify hardware.
• 1’s complement is rarely used today but appears in legacy systems.

2. Binary Adders: From Half-Adder to Ripple-Carry Adder

Half-Adder (HA)

Definition: Adds two single bits (A, B) and produces Sum (S) and Carry (C). Truth Table:

| A | B | S | C |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |

Logic Equations:

• $S=A\oplus B$ (XOR)
• $C=A\cdot B$ (AND)

Circuit Diagram:

Full-Adder (FA)

Definition: Adds three bits (A, B, C_in) and produces Sum (S) and Carry-out (C_out). Truth Table:

| A | B | C_in | S | C_out |
|---|---|------|---|-------|
| 0 | 0 |  0   | 0 |   0   |
| 0 | 0 |  1   | 1 |   0   |
| 0 | 1 |  0   | 1 |   0   |
| 0 | 1 |  1   | 0 |   1   |
| 1 | 0 |  0   | 1 |   0   |
| 1 | 0 |  1   | 0 |   1   |
| 1 | 1 |  0   | 0 |   1   |
| 1 | 1 |  1   | 1 |   1   |

Logic Equations:

• $S=A\oplus B\oplus C_{in}$
• $C_{out}=(A\cdot B)+(B\cdot C_{in})+(A\cdot C_{in})$

Circuit Diagram:

Ripple-Carry Adder (RCA)

Definition: Cascades full-adders to add n-bit numbers. Example: 4-bit RCA for A = 1011, B = 0101:

   1 0 1 1 (A)
+  0 1 0 1 (B)
-----------
  1 0 0 0 0 (Sum)

Circuit Diagram (4-bit RCA):

flowchart LR
    A0 & B0 --> FA1["Full-Adder 1"]
    FA1 --> S0
    FA1 --> C1
    A1 & B1 & C1 --> FA2["Full-Adder 2"]
    FA2 --> S1
    FA2 --> C2
    A2 & B2 & C2 --> FA3["Full-Adder 3"]
    FA3 --> S2
    FA3 --> C3
    A3 & B3 & C3 --> FA4["Full-Adder 4"]
    FA4 --> S3
    FA4 --> C4
    C4 --> C_out

Drawback: Slow for large n due to propagation delay (carry ripples through all FAs).

3. Subtraction Using Complements

Why Complements?

Subtraction is expensive in hardware. Instead, we use:

1. 1’s Complement: Flip all bits (e.g., 0101 → 1010).
2. 2’s Complement: 1’s complement + 1 (e.g., 0101 → 1011).
3. 9’s/10’s Complement: Used in decimal systems (e.g., 9999 – 1234 = 8765 via 10’s complement).

Subtraction Using 2’s Complement (Binary)

Steps:

1. Find 2’s complement of subtrahend (B).
2. Add it to minuend (A).
3. Discard final carry (if any).

Example: Subtract B = 0101 (5) from A = 0111 (7).

   A = 0111 (7)
   B = 0101 (5)
   2’s(B) = 1011
   A + 2’s(B) = 0111 + 1011 = 10010 (discard carry)
   Result = 0010 (2) ✅

Circuit Implementation: Use a subtractor circuit (which is just an adder with inverted inputs):

Subtraction Using 10’s Complement (Decimal)

Example: Subtract 78.35 from 739.57.

1. Find 10’s complement of 78.35:
   • Invert digits: 21.64
   • Add 1: 21.65
2. Add to 739.57:

     739.57
   + 21.65
   --------
    761.22
   

3. If no overflow, result is correct. If overflow, add 100 to result: 761.22 + 100 = 861.22 (but here, no overflow, so result is 761.22).

Real-World Tie-In:

• Khalti/ESewa transactions use modular arithmetic (similar to complements) to verify amounts.
• Bank loan interest calculations often use complementary methods for efficiency.

4. Arithmetic Logic Unit (ALU)

Definition: A combinational circuit that performs arithmetic (+, -, ×, ÷) and logical (AND, OR, NOT) operations. Block Diagram:

flowchart LR
    A --> ALU["ALU"]
    B --> ALU
    OpCode --> ALU
    ALU --> Result
    ALU --> Flags["Zero/Overflow"]

Example Operations:

Real-World Example:

• CPU ALUs (e.g., in Intel’s Core i7) use 2’s complement arithmetic for all operations.
• Google’s search algorithms rely on bitwise operations (AND/OR/XOR) for data compression.

5. Comparison: Complement Methods

6. Real-World Applications

1. eSewa/Khalti (Digital Payments)

• Idea Used: 2’s complement arithmetic for transaction validation.
• How:
  • When you pay ₹500, the system checks the complement of the amount to detect fraud (e.g., 500 vs. ~500 + 1).
  • If the complement doesn’t match, the transaction is flagged.

2. Daraz Order Processing

• Idea Used: Priority queues (like ripple-carry adders) for order fulfillment.
• How:
  • Orders are processed in priority order (like carries propagating in an adder).
  • High-priority orders (e.g., "Deliver by 5 PM") are handled first, similar to how a ripple-carry adder processes the most significant bits first.

3. NTC Electricity Billing

• Idea Used: 9’s complement for decimal subtraction in billing systems.
• How:
  • When calculating Total Consumption – Previous Reading, the billing software uses 10’s complement to avoid complex subtraction circuits.
  • Example: 500 units – 450 units = 50 units (using 10’s complement method).

Exam Tip

What Examiners Look For

1. Circuit Design:

   • Draw full-adder/subtractor circuits with correct gate symbols.
   • Label all inputs/outputs (e.g., A, B, C_in, Sum, C_out).
   • Common Mistake: Forgetting to include the carry-in in a full-adder.

2. Complement Arithmetic:

   • Show step-by-step conversion (e.g., 1’s → 2’s).
   • For decimal, always add 1 after inverting digits.
   • Common Mistake: Forgetting to discard the final carry in 2’s complement.

3. State Diagrams/Timing Diagrams:

   • If asked about sequential circuits (e.g., counters), draw:
     • State diagram (with states and transitions).
     • Timing diagram (showing clock, inputs, outputs).
   • Common Mistake: Missing the initial state in the diagram.

4. Real-World Problems:

   • For subtraction questions, always:
     1. Convert to complement.
     2. Add.
     3. Handle overflow.
   • Example Question: "Subtract (1001.11)₂ – (1010.10)₂ using 2’s complement." Solution:

     Minuend (A) = 1001.11
     Subtrahend (B) = 1010.10
     2’s(B) = 0101.10 (flip) + 1 = 0101.11
     A + 2’s(B) = 1001.11 + 0101.11 = 10011.10 → Discard carry → 0011.10 (Result)
     

5. Shortcut for Exams:

   • Memorize the 4-bit adder/subtractor truth tables.
   • For JK flip-flop questions, always draw:
     • Characteristic table.
     • Excitation table.
     • Timing diagram (showing clock edges).

Practice Problems (Exam-Style)

1. Design a 4-bit subtractor using full-adders (Hint: Use 2’s complement).
2. Subtract (1101.10)₂ – (0110.01)₂ using both 1’s and 2’s complement.
3. Draw the timing diagram for a ripple-carry adder adding 1011 + 0101.
4. Explain how a CPU ALU uses 2’s complement for subtraction. (Hint: Mention "invert and add 1".)