Microprocessor and Computer ArchitectureUnit 109 min read
Arithmetic & Logic Operations: ALU, Flags, Pipelining, Micro-ops & Real-World Math
Unit 10 of Microprocessor and Computer Architecture covers the Arithmetic Logic Unit (ALU), arithmetic and logic micro-operations, flags, arithmetic pipelines, and microprogramming for arithmetic operations—explaining how CPUs perform math, comparisons, and optimizations like pipelining, with real-world examples from b
TAKEAWAYS:
- The ALU executes arithmetic (add, subtract, multiply) and logic (AND, OR, NOT) operations, and sets flags (Zero, Carry, Sign, Overflow) to reflect results.
- Arithmetic micro-operations break down complex operations (e.g., subtraction as two’s complement addition) into low-level hardware steps.
- Pipelining speeds up arithmetic by overlapping instruction stages (fetch, decode, execute), but introduces hazards (data, control, structural).
- Microprogramming uses a control store to sequence micro-operations, simplifying complex arithmetic like multiplication/division.
- Real-world math: Banks use compound interest (arithmetic pipeline), eSewa validates transactions via bitwise checks (logic ops), and Daraz sorts orders using comparison flags.
1. The Arithmetic Logic Unit (ALU): The CPU’s Math & Logic Engine
The ALU is the heart of the CPU, performing all arithmetic and logic operations. It takes two operands (from registers, memory, or immediate values) and produces a result, alongside status flags (Zero, Carry, Sign, Overflow).
Key ALU Operations
| Category | Operations | Example Use Case |
|---|---|---|
| Arithmetic | ADD, SUB, INC, DEC, MUL, DIV, CMP | Calculating loan interest (banks), eSewa transaction totals. |
| Logic | AND, OR, XOR, NOT, SHIFT (<<, >>) | Validating transaction hashes (Khalti), compressing data (Daraz). |
| Bitwise | TEST, SET, CLEAR, ROTATE | Error detection in NTC network packets. |
How ALU Works: A Step-by-Step Trace
Consider the instruction ADD B, C (add registers B and C):
- Inputs: B =
00001010(10), C =00000101(5). - ALU Operation: Performs binary addition:
00001010 (B)
00000101 (C)
00001111 (15)
- Flags Set:
- Zero (Z): 0 (result ≠ 0)
- Carry (CY): 0 (no overflow beyond 8 bits)
- Sign (S): 0 (MSB = 0, positive)
- Overflow (OV): 0 (no signed overflow)
2. Arithmetic Micro-Operations: Breaking Down Math
Micro-operations are the low-level hardware steps that implement high-level instructions. For example, subtraction is implemented as two’s complement addition to simplify hardware.
Example: Subtraction as Two’s Complement Addition
To compute A = B - C:
- Find Two’s Complement of C:
- Invert bits of C:
~C - Add 1:
~C + 1 - Example: C =
00000101(5)~C=11111010~C + 1=11111011(two’s complement of 5)
- Invert bits of C:
- Add B to Two’s Complement of C:
B = 00001010 (10)
~C + 1 = 11111011 (-5)
Result = 00000011 (11)- The **Carry flag (CY)** is discarded (it’s the borrow bit). - **Flags updated**: Z=0, S=0, OV=0 (no overflow).
Micro-Operations for Multiplication (8085 Example)
The 8085 uses shift-and-add for multiplication:
stateDiagram-v2
[*] --> Initialize: A=0, B=multiplicand, C=multiplier
Initialize --> Check_LSB: Is LSB of C = 1?
Check_LSB --> Add: Yes --> A = A + B
Add --> Shift: Shift B right, shift C right
Shift --> Check_LSB
Check_LSB --> End: No --> [*]Example: Multiply A = 3 (0011) and B = 4 (0100):
- Initial: A=0000, B=0100, C=0100
- Iteration 1: LSB(C)=0 → Shift → A=0000, B=0010, C=0010
- Iteration 2: LSB(C)=0 → Shift → A=0000, B=0001, C=0001
- Iteration 3: LSB(C)=1 → A = 0000 + 0001 = 0001 → Shift → A=0011 (3), B=0000, C=0000
- Result: A = 12 (00001100), but 8085 stores only lower 8 bits → Overflow occurs (actual result = 12, but only 4 is stored).
3. Arithmetic Pipeline: Speeding Up Math with Overlapping
Pipelining divides arithmetic operations into stages, allowing multiple operations to progress simultaneously. The 8085 ALU pipeline has stages:
- Fetch: Get operands from registers/memory.
- Decode: Determine operation (ADD/SUB/etc.).
- Execute: Perform ALU operation.
- Writeback: Store result and update flags.
Pipeline Hazards in Arithmetic
| Hazard Type | Cause | Example | Solution |
|---|---|---|---|
| Data Hazard | Dependent instructions overlap. | ADD A, B; SUB A, C (A needed before writeback). |
Forwarding (bypass) or stall. |
| Control Hazard | Branches/jumps disrupt flow. | CMP B, C; JZ label (flags not ready). |
Delayed branching or speculative execution. |
| Structural Hazard | Resource conflict. | Two ALU ops need the same adder. | Dual ALUs or reservation stations. |
Example: Pipeline Stall in Subtraction
sequenceDiagram
participant IF as Instruction Fetch
participant ID as Instruction Decode
participant EX as Execute
participant WB as Writeback
IF->>ID: Fetch SUB A,B
ID->>EX: Decode SUB
EX->>WB: Execute (A = B - C)
WB->>IF: Writeback (update flags)
IF->>ID: Fetch ADD A,D (needs A from previous SUB)
Note right of IF: Stall! A not yet written back.
ID-->>IF: Stall cycle inserted
A labelled diagram showing fetch, decode, execute, memory, and writeback stages with data/control hazards marked. (Image: Sandstorm de, CC BY-SA 4.0, via Wikimedia Commons)
4. Microprogramming for Arithmetic: Controlling the ALU
Microprogramming uses a control store (ROM) to sequence micro-operations. Each high-level instruction (e.g., MUL) is broken into micro-instructions.
Microprogram for FETCH Operation (8085)
| Micro-instruction | Operation | Flags Updated |
|---|---|---|
| 1 | Load PC into MAR | None |
| 2 | Increment PC | None |
| 3 | Read memory (IR ← M[MAR]) | None |
| 4 | Load IR into instruction register | None |
| 5 | Decode opcode | None |
Symbolic Microprogram for ADD A, B:
Step 1: Load A and B into ALU inputs
Step 2: ALU ← ADD
Step 3: A ← ALU result
Step 4: Set Z, S, CY, OV flags
5. Real-World Applications: Where Math Meets Microprocessors
Example 1: Compound Interest Calculation (Nepal Bank Limited)
- Concept: Arithmetic pipeline for repeated multiplication/addition.
- How it works:
- Formula:
- 8085 ALU steps:
- Load principal .
- Multiply by rate (using shift-and-add).
- Repeat for years.
- Optimization: Pipelining allows parallel calculation for multiple accounts.
Example 2: Transaction Validation (eSewa)
- Concept: Bitwise logic operations (XOR, AND) for checksums.
- How it works:
- eSewa generates a hash of transaction details using XOR:
hash = amount ^ merchant_id ^ timestamp - The 8085 ALU performs
XOR A, Bto validate the hash before processing payment.
- eSewa generates a hash of transaction details using XOR:
Example 3: Order Processing (Daraz)
- Concept: Comparison flags (Z, S) for sorting orders.
- How it works:
- Daraz sorts orders by priority using
CMP(compare):CMP priority, threshold ; Sets Z flag if equal JZ process_high_priority ; Jump if Z=1 - The ALU’s Sign flag helps sort negative/positive values.
- Daraz sorts orders by priority using
6. Exam Tip: How to Score Full Marks
For arithmetic micro-operations:
- Always show binary examples (e.g.,
ADD 5 + 3in binary). - Explain flag updates (Z, CY, S, OV) explicitly.
- Example: "For
SUB B, the ALU computes two’s complement of B and adds it to A. The Carry flag is discarded, and Overflow is set if signs of A and B differ but result’s sign matches B."
- Always show binary examples (e.g.,
For pipelining:
- Draw a timeline diagram showing stages and hazards.
- Compare pipelined vs. non-pipelined execution times (e.g., 4 cycles vs. 12 cycles for 4 instructions).
- Mention hazard solutions (stalls, forwarding).
For microprogramming:
- Write symbolic micro-instructions in a table.
- Link each step to control signals (e.g., "Load MAR" → "Set MARLE=1").
- Example: "The FETCH microprogram requires 5 micro-ops: load PC, increment PC, read memory, load IR, and decode."
Real-world questions:
- Relate to banks (interest), e-commerce (sorting), or telecom (error checking).
- Example: "Ncell uses XOR in CRC checks to detect corrupted SMS packets. The 8085 ALU’s XOR operation compares the received CRC with computed CRC, setting the Zero flag if they match."
Final Note: Master the binary traces, flag logic, and pipeline diagrams—these are the highest-scoring parts of the exam!
Based on the TU BIT syllabus for Microprocessor and Computer Architecture (BIT151), unit 10.
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