Virtual Memory: Paging, Swapping, TLB, Segmentation

TAKEAWAYS:

• Virtual memory lets programs run with more memory than the system physically has by using disk as an extension of RAM.
• Paging divides memory into fixed-size blocks (pages) and frames, while segmentation uses variable-size blocks (segments).
• The Translation Lookaside Buffer (TLB) speeds up address translation by caching recent mappings.
• Swapping moves entire processes between RAM and disk to free up memory for active tasks.
• Memory-mapped I/O treats devices as memory locations, simplifying hardware interaction.
• Virtual memory improves multitasking but introduces overhead and potential performance bottlenecks.

1. Introduction to Virtual Memory

Virtual memory is a memory management technique that allows a computer to compensate for physical memory shortages by temporarily transferring data from RAM to disk storage. It gives the illusion to programs that they have contiguous, dedicated memory, even when the system’s physical RAM is limited.

Why Virtual Memory?

• Enables multitasking: Multiple programs can run simultaneously without crashing due to memory conflicts.
• Memory isolation: Each process believes it has exclusive access to memory, improving security and stability.
• Efficient resource usage: Frees up RAM for active tasks while inactive processes reside on disk.

Key Concepts

• Logical Address: The address generated by a CPU for a process (e.g., 0x1234).
• Physical Address: The actual memory location in RAM (e.g., 0x5678).
• Memory Management Unit (MMU): Hardware that translates logical addresses to physical addresses.

2. Paging: Dividing Memory into Fixed-Sized Blocks

Paging splits both physical memory (RAM) and logical memory into fixed-size blocks called frames (physical) and pages (logical). Each page is of the same size (e.g., 4 KB).

How Paging Works

1. The CPU generates a logical address (e.g., 1000).
2. The address is split into:
   • Page number (high-order bits, e.g., 1).
   • Offset (low-order bits, e.g., 000).
3. The Page Table maps page numbers to physical frame numbers.
4. The MMU combines the frame number with the offset to get the physical address.

Example: Address Translation in Paging

Suppose:

• Page size = 4 KB = 2¹² bytes → 12 bits for offset.
• Logical address = 0x1234 (4660 in decimal).
• Page number = 0x12 (18 in decimal).
• Offset = 0x34 (52 in decimal).
• Page table maps page 18 to frame 42.

Logical Address: 0x1234
| Page Number (12 bits) | Offset (12 bits) |
|       0x12           |      0x34        |
Page Table: 18 → 42
Physical Address = Frame 42 + Offset 0x34 = 0x2A34

Visual: Paging Address Translation

3. Segmentation: Dividing Memory into Variable-Sized Blocks

Unlike paging, segmentation divides memory into variable-sized blocks called segments. Each segment corresponds to a logical unit (e.g., code, data, stack).

How Segmentation Works

1. The CPU generates a logical address with:
   • Segment number (e.g., 0 for code, 1 for data).
   • Offset within the segment.
2. The Segment Table maps segment numbers to base and limit values.
   • Base: Starting physical address of the segment.
   • Limit: Size of the segment.
3. The MMU checks if the offset is within the segment’s limit. If yes, it calculates the physical address as Base + Offset.

Example: Address Translation in Segmentation

Suppose:

• Segment 0 (code) has base 0x1000 and limit 0x1000.
• Logical address = 0x0000 (segment 0, offset 0).
• Physical address = 0x1000 + 0 = 0x1000.

Logical Address: 0x0000 (Segment 0, Offset 0)
Segment Table: Segment 0 → Base: 0x1000, Limit: 0x1000
Physical Address = 0x1000 + 0 = 0x1000

Comparison: Paging vs. Segmentation

4. Translation Lookaside Buffer (TLB)

The TLB is a hardware cache that stores recent page table entries to speed up address translation. It reduces the time spent looking up the page table in RAM.

How TLB Works

1. CPU generates a logical address → extract page number.
2. Check if the page number is in the TLB.
   • Hit: Use the cached frame number → fast translation.
   • Miss: Look up the page table in RAM → update TLB → proceed.
3. If the page is not in RAM (a page fault), the OS loads it from disk.

Example: TLB Hit/Miss

Suppose:

• Logical address = 0x1234 (page 18).
• TLB contains 18 → 42.
• TLB Hit: Use frame 42 → physical address 0x2A34.
• If TLB misses, the OS fetches the page table entry from RAM.

Visual: TLB Operation

sequenceDiagram
    participant CPU
    participant TLB
    participant PageTable
    participant Disk

    CPU->>TLB: Check page 18
    alt TLB Hit
        TLB-->>CPU: Frame 42
    else TLB Miss
        TLB->>PageTable: Fetch frame for page 18
        PageTable-->>TLB: Frame 42
        TLB-->>CPU: Frame 42 (update cache)
    end

5. Swapping: Moving Processes Between RAM and Disk

Swapping is the process of moving an entire process (or parts of it) between RAM and disk to free up memory for other tasks.

How Swapping Works

1. The OS identifies a process that is not actively running (e.g., idle or in the background).
2. It writes the process’s memory pages to disk (swap space).
3. The process’s memory is removed from RAM, freeing up space.
4. When the process needs to run again, it is loaded back into RAM from disk.

Example: Swapping in a Multitasking OS

Suppose:

• RAM has 8 GB, but 3 processes (A, B, C) are running, each needing 4 GB.
• Process A is idle for 5 minutes.
• The OS swaps A to disk, freeing 4 GB for other tasks.

Advantages of Swapping

• Increases the number of processes that can run simultaneously.
• Prevents system crashes due to memory exhaustion.

Disadvantages of Swapping

• Overhead: Moving large processes to/from disk is slow.
• Thrashing: Excessive swapping reduces system performance.
• Disk I/O Bottleneck: Frequent disk access can slow down the system.

6. Memory-Mapped I/O

Memory-mapped I/O treats hardware devices (e.g., GPU, USB ports) as memory locations. Instead of using special I/O instructions, the CPU accesses devices like RAM.

How Memory-Mapped I/O Works

1. The OS reserves a range of physical memory addresses for devices.
2. When a program writes to a memory address in this range, the hardware interprets it as an I/O operation.
3. Example: Writing to 0xFF00 might trigger a USB data transfer.

Example: Accessing a GPU via Memory-Mapped I/O

Suppose:

• GPU is mapped to physical addresses 0xA0000000 to 0xAFFFFFFF.
• A program writes 0xA0000000 = 0xDEADBEEF.
• The GPU receives the data and renders it.

Advantages

• Simplifies programming (no separate I/O instructions).
• Faster than traditional I/O (uses memory access speed).

Disadvantages

• Risk of accidental hardware access if memory protection is weak.
• Complexity in memory management.

7. Virtual Memory Techniques: Paging vs. Segmentation

8. Real-World Applications of Virtual Memory

In the Real World

1. Daraz (Nepal’s E-Commerce Giant)

   • Idea: Virtual memory allows Daraz to handle thousands of concurrent user requests without crashing.
   • How: When a user browses products, Daraz’s backend uses virtual memory to load only the necessary data into RAM while keeping inactive pages on disk. If a user abandons their cart, the OS swaps less active pages to disk, freeing RAM for new orders.
   • Worked Example: During the "Daraz Festival," servers use virtual memory to manage spikes in traffic. If 10,000 users simultaneously view the same product page, the OS pages only the active users’ data into RAM, while others wait on disk. This prevents system overload.

2. Ncell (Nepal’s Mobile Network)

   • Idea: Virtual memory enables Ncell’s call centers to handle multiple calls simultaneously.
   • How: Each call is a process that requires memory. Virtual memory allows Ncell to allocate RAM dynamically to active calls while swapping inactive calls to disk. If a user’s call drops, the OS can quickly swap in a new call’s data.
   • Worked Example: During peak hours (e.g., 6 PM), Ncell’s servers use paging to manage 50,000 concurrent calls. The OS ensures that only the most recent call data is in RAM, while older calls are paged out to disk. This reduces RAM usage and prevents call drops.

3. NEPSE (Nepal Stock Exchange)

   • Idea: Virtual memory helps NEPSE handle real-time stock trading data.
   • How: Trading algorithms require fast access to market data. Virtual memory allows NEPSE to load only the active trading data into RAM while keeping historical data on disk. If a trader places a large order, the OS pages in the necessary data quickly.
   • Worked Example: During high-volume trading (e.g., during IPOs), NEPSE’s servers use segmentation to isolate different trading processes. Each trader’s data is in a separate segment, and the OS uses paging to load only the relevant segments into RAM. This ensures smooth trading even with limited physical memory.

9. Exam Tips for Virtual Memory

1. Understand the Difference Between Logical and Physical Addresses

   • Always explain how the MMU translates logical addresses to physical addresses in paging/segmentation.
   • Example: For a logical address 0x1234 in a 4 KB page system, show how it splits into page number and offset.

2. Draw Diagrams for Address Translation

   • Include a page table, TLB, and the translation process in your answers.
   • Example:

     Logical Address: 0x1234 → Page 18, Offset 0x34
     Page Table: 18 → Frame 42
     Physical Address: 0x2A34
     

3. Compare Paging and Segmentation

   • Highlight pros/cons (e.g., external fragmentation in segmentation, internal fragmentation in paging).
   • Use a table like the one above.

4. Explain TLB with a Sequence Diagram

   • Show how a TLB hit/miss affects address translation speed.
   • Example: Draw a sequence diagram with CPU, TLB, and Page Table.

5. Discuss Swapping and Thrashing

   • Explain how swapping works and why excessive swapping (thrashing) harms performance.
   • Mention real-world examples like Daraz’s server load during sales.

6. Relate Virtual Memory to Real-World Scenarios

   • Connect concepts to apps like WhatsApp (multitasking), Google Maps (memory-mapped I/O for GPU rendering), or banks (loan interest calculations using memory for large datasets).
   • Example: "A bank’s loan processing system uses virtual memory to handle thousands of customer records. Only active loan applications are in RAM, while inactive ones are paged to disk."

7. Practice Worked Examples

   • Solve problems like:
     • "Given a logical address 0xABCD in a 2 KB page system, find the physical address if the page table maps page ABC to frame 123."
     • "Explain how a TLB miss affects the address translation time."

8. Avoid Common Mistakes

   • Don’t confuse paging (fixed-size blocks) with segmentation (variable-size blocks).
   • Don’t forget to mention the MMU in address translation explanations.
   • Always include the offset in paging calculations.

mindmap
  root((Virtual Memory))
    PhysicalRAM[RAM (Limited)]
    DiskStorage[Disk (Extends RAM)]
    Processes[Multiple Processes]
      ProcessA[Active (In RAM)]
      ProcessB[Inactive (On Disk)]
    OSRole[OS Manages Swapping/Paging]
    Hardware[MMU + TLB Speed Up Access]
    Paging[Fixed-Sized Pages]
    Segmentation[Variable-Sized Segments]
    TLB[Cache for Page Tables]
    Swapping[Processes Moved to Disk]