Flip-Flops & Latches: Types, Triggering, Counters & Registers

TAKEAWAYS:

• Flip-flops are 1-bit memory elements that store state until triggered, while latches are level-sensitive and transparent; flip-flops are edge-triggered and opaque.
• The JK flip-flop resolves the indeterminate state problem of SR flip-flops by introducing a toggle mode (J=K=1).
• Triggering types (level, positive/negative edge) determine when a flip-flop updates its state, critical for synchronous/asynchronous designs.
• Counters and registers use cascaded flip-flops (e.g., T-flipflops for binary counters) to implement sequential logic in real systems like eSewa’s transaction IDs or Ncell’s call duration timers.
• Race-around condition in SR flip-flops is avoided in JK/T flip-flops via feedback or dedicated control inputs.
• Practical applications include shift registers (data transmission), traffic light controllers (state machines), and memory units (CPU registers).

1. Introduction: Why Flip-Flops and Latches?

Flip-flops and latches are the basic memory elements in digital circuits. Unlike combinational circuits (which depend only on current inputs), sequential circuits (like counters, registers, and state machines) rely on memory to retain state between clock cycles. This memory is implemented using flip-flops or latches.

Key Differences: Latches vs. Flip-Flops

classDiagram
    class Latch {
        +Level-triggered (transparent)
        +No clock edge required
        +Asynchronous operation
        +Used in memory, I/O buffers
    }
    class FlipFlop {
        +Edge-triggered (opaque)
        +Requires clock edge
        +Synchronous operation
        +Used in counters, registers, CPUs
    }
    Latch --> "Derived from" BasicGates
    FlipFlop --> "Derived from" Latch
    FlipFlop --> "More reliable" Latch

2. Basic Flip-Flop: SR Latch (Set-Reset)

The simplest flip-flop is the SR (Set-Reset) latch, built using cross-coupled NOR or NAND gates. It has two stable states:

• Set (Q=1): Output follows the S (Set) input.
• Reset (Q=0): Output follows the R (Reset) input.

Problem: Indeterminate State

If S=R=1, the outputs become unstable (race-around condition). This is why SR latches are rarely used alone in practical designs.

   S ----|>|----+
          |      |
   R ----|>|----+---- Q (Output)
          |      |
          +------|
               |
               Q' (Complement)

Truth Table for SR Latch (NOR-based):

Why can’t we have S=R=1?

• In NOR-based SR latches, S=R=1 forces both outputs to 0, violating the complement rule (Q' = NOT Q).
• This creates a race condition where outputs oscillate until power is removed.

3. Clocked SR Flip-Flop

To make the SR latch synchronous, we add a clock (CLK) input and use gating (AND/NAND) to enable updates only at the clock edge.

   CLK ----|>|----+
           |      |
   S ----|>|----+---- Q
           |      |
   R ----|>|----+
           |      |
           +------|
               |
               Q'

Truth Table (Positive Edge-Triggered):

Problem Persists: The S=R=1 issue remains. This leads to the JK flip-flop, which eliminates this problem.

4. JK Flip-Flop: The Universal Flip-Flop

The JK flip-flop adds two new inputs (J and K) and resolves the indeterminate state by introducing a toggle mode:

• If J=K=1, the flip-flop toggles its state (Q → Q').
• This eliminates the forbidden state.

How It Works

• Built using SR flip-flop + feedback or master-slave configuration.
• Triggering: Can be level-triggered (like latches) or edge-triggered (synchronous).

   CLK ----|>|----+
           |      |
   J ----|>|----+---- Q
           |      |
   K ----|>|----+
           |      |
           +------|
               |
               Q'

Truth Table (Positive Edge-Triggered):

Advantages Over SR Flip-Flop: ✅ No forbidden state (J=K=1 is valid). ✅ Can act as T flip-flop (toggle-only) by tying J=K=1. ✅ Used in counters, registers, and state machines.

5. D Flip-Flop: The Data Latch

The D (Delay) flip-flop has only one data input (D). Its output Q follows D at the clock edge.

Applications:

• Data storage (registers, memory).
• Shift registers (serial data transmission).
• Debouncing (cleaning up noisy signals).

   CLK ----|>|----+
           |      |
   D ----|>|----+---- Q
           |      |
           +------|
               |
               Q'

Truth Table (Positive Edge-Triggered):

Example: Storing a Bit in a Register

• Scenario: eSewa needs to store a transaction approval bit (1=approved, 0=pending).
• Solution: Use a D flip-flop triggered by a clock pulse when the transaction is processed.
• Operation:
  • At clock edge, if D=1 (approved), Q=1.
  • If D=0 (pending), Q=0.

6. T Flip-Flop: The Toggle Flip-Flop

The T (Toggle) flip-flop changes its state every clock pulse when T=1.

How It’s Built

• Can be derived from a JK flip-flop by tying J=K=T.
• Used in binary counters (e.g., counting seconds in a digital clock).

   CLK ----|>|----+
           |      |
   T ----|>|----+---- Q
           |      |
           +------|
               |
               Q'

Truth Table:

Problem with T Flip-Flop:

• Race-around condition if not properly designed (e.g., using JK flip-flop with J=K=T).
• Solution: Use master-slave configuration or asynchronous clear.

Example: Binary Counter (3-bit)

• Scenario: Counting Ncell call duration in seconds (0 to 7).
• Design: Use 3 T flip-flops cascaded.
• Operation:
  • Each flip-flop toggles on the next clock pulse.
  • Outputs form a binary count (000 → 001 → 010 → ... → 111).

   CLK ----|>|----+----|>|----+----|>|---- Q2
           |      |    |      |    |      |
           T1    T2  T3    T2  T3    T1    Q1
           |      |    |      |    |      |
           +------+    +------+    +------+

State Transition Table:

7. Triggering Mechanisms

Flip-flops can be triggered in three ways:

Example: Traffic Light Controller (State Machine)

• Scenario: Kathmandu traffic lights change every 60 seconds.
• Design:
  • Use JK flip-flops with negative edge triggering.
  • Each flip-flop represents a state (Red → Green → Yellow).
  • A timer circuit generates clock pulses every 60 seconds.

stateDiagram-v2
    [*] --> Red: Start
    Red --> Green: After 60s
    Green --> Yellow: After 30s
    Yellow --> Red: After 10s
    Red --> [*]

8. Flip-Flops in Registers and Counters

flowchart LR
    subgraph Register
        DFF1["D Flip-Flop"] -->|"Q0"| DFF2["D Flip-Flop"]
        DFF2 -->|"Q1"| DFF3["D Flip-Flop"]
        DFF3 -->|"Q2"| DFF4["D Flip-Flop"]
        DFF4 -->|"Q3"| Output
    end
    CLK --> DFF1
    CLK --> DFF2
    CLK --> DFF3
    CLK --> DFF4
    Data --> DFF1

A. Registers (Parallel Data Storage)

• A register is a group of D flip-flops storing n bits.
• Example: Storing 4-bit data (1011) in a register.

   CLK ----|>|----+----|>|----+----|>|----+----|>|---- Q3
           |      |    |      |    |      |    |      |
   D3 ----|>|----+    D2    D1    D0    Q2    Q1    Q0
           |      |    |      |    |      |
           +------+    +------+    +------+

Operation:

1. Load data 1011 into D3 D2 D1 D0.
2. At clock edge, Q3 Q2 Q1 Q0 = 1011.
3. Shift right: Next clock pulse moves data to Q2 Q1 Q0 (serial output).

Real-World Example: eSewa Transaction ID

• eSewa generates a unique 8-bit ID for each transaction.
• A 4-bit register (like above) can store part of this ID.
• Clock pulse: Triggered when a new transaction is processed.

B. Counters (Sequential Counting)

Counters use T flip-flops or JK flip-flops to count pulses.

Example: 3-bit Binary Counter (0 to 7)

   CLK ----|>|----+----|>|----+----|>|---- Q2 (MSB)
           |      |    |      |    |      |
           T1    T2  T3    T2  T3    T1    Q1
           |      |    |      |    |      |
           +------+    +------+    +------+

Operation:

• Each flip-flop toggles when the less significant flip-flop rolls over (e.g., Q0 toggles every clock, Q1 toggles when Q0 goes from 1→0).

Real-World Example: Ncell Call Duration Timer

• Ncell counts call duration in seconds (0-59).
• A 6-bit counter (0 to 63) can track time.
• Overflow: After 60 seconds, reset and increment minutes.

9. Flip-Flop Applications in Real World

A. eSewa: Transaction Processing Queue

• Problem: eSewa needs to track pending transactions before approval.
• Solution: Use a shift register (D flip-flops) to store transaction IDs.
• How it works:
  1. Each transaction ID is loaded into the register.
  2. A clock pulse shifts the ID to the next flip-flop.
  3. The rightmost flip-flop outputs the oldest transaction for approval.

B. Ncell: Call Duration Timer

• Problem: Ncell must measure call time accurately.
• Solution: Use a binary counter (T flip-flops) with a 1Hz clock.
• How it works:
  1. Each flip-flop toggles every second.
  2. The 6-bit output represents 0-63 seconds.
  3. When it overflows, a decade counter increments minutes.

C. Daraz: Order Processing System

• Problem: Daraz needs to track order status (Pending → Processing → Shipped).
• Solution: Use a state machine with JK flip-flops.
• How it works:
  • Each flip-flop represents a state.
  • A clock pulse triggers transitions (e.g., Pending → Processing).

10. Exam Tip: How to Score Full Marks

1. Draw Logic Diagrams Correctly

   • Use standard gate symbols (no hand-drawn approximations).
   • Label clock, inputs, and outputs clearly.
   • Example: For a JK flip-flop, show master-slave configuration if asked.

2. Explain Triggering Mechanisms

   • Always specify positive/negative edge or level-triggered.
   • Example: "This D flip-flop is positive edge-triggered, so Q updates only at the rising edge of CLK."

3. Compare Flip-Flop Types

   • Use a table to highlight differences (e.g., SR vs. JK vs. D).
   • Example:

     Flip-Flop	Inputs	Forbidden State	Toggle Mode
     SR	S, R	S=R=1	No
     JK	J, K	None	Yes (J=K=1)
     D	D	None	No

4. Solve Counter/Register Problems Step-by-Step

   • For a 3-bit counter, show:
     1. Flip-flop type (e.g., T flip-flop).
     2. Connection logic (e.g., T1=CLK, T2=Q1', T3=Q2'Q1').
     3. State transition table.

5. Avoid Common Mistakes

   • ❌ Forgetting to mention clock edge in explanations.
   • ❌ Drawing asynchronous inputs (like preset/clear) without labeling.
   • ❌ Assuming all flip-flops are edge-triggered (some are level-triggered).

Example Exam Question & Answer: Q: Design a 3-bit synchronous binary counter using JK flip-flops. A:

1. Flip-Flop Choice: Use JK flip-flops (since T flip-flops can be derived from JK).
2. Connections:
   • J1=K1=1 (Toggles every clock).
   • J2=K2=Q1' (Toggles when Q1=1).
   • J3=K3=Q2'Q1' (Toggles when Q2Q1=11).
3. Logic Diagram:

      CLK ----|>|----+----|>|----+----|>|---- Q2
              |      |    |      |    |      |
              J1    K1  J2    K2  J3    K3  Q1
              |      |    |      |    |      |
              +------+    +------+    +------+
   

4. State Table:

   CLK	Q2 Q1 Q0
   0	0 0 0
   1	0 0 1
   2	0 1 0
   ...	...
   8	1 0 0

Final Note: Flip-flops are the backbone of sequential logic. Master their types, triggering, and applications (counters, registers, state machines) to excel in exams and real-world designs like eSewa, Ncell, and Daraz systems. Always draw diagrams and label them properly—this is where full marks are won!