Design 1 × 4 D multiplexer.

Design of a 4×1 Multiplexer

A 4×1 Multiplexer (MUX) is a combinational logic circuit that selects one of the four input lines and directs it to a single output line based on the binary value of the select lines (S₁, S₀). The truth table for a 4×1 MUX is as follows:

Logic Expression

The output $Y$ of the 4×1 MUX can be expressed using the minterm expansion method:

$$Y=\overline{S_1}\cdot \overline{S_0}\cdot I_0+\overline{S_1}\cdot S_0\cdot I_1+S_1\cdot \overline{S_0}\cdot I_2+S_1\cdot S_0\cdot I_3$$

Circuit Design

The 4×1 MUX can be constructed using AND gates, OR gates, and NOT gates as follows:

1. Generate minterms using AND gates:

   • $\overline{S_1}\cdot \overline{S_0}\cdot I_0$
   • $\overline{S_1}\cdot S_0\cdot I_1$
   • $S_1\cdot \overline{S_0}\cdot I_2$
   • $S_1\cdot S_0\cdot I_3$

2. Combine the minterms using an OR gate to produce the final output $Y$.

Logic Diagram

The circuit can be represented as:

graph TD
    subgraph Inputs
        I0["I₀"]
        I1["I₁"]
        I2["I₂"]
        I3["I₃"]
        S1["S₁"]
        S0["S₀"]
    end

    subgraph NOT Gates
        NOT1[/¬/] -->|"S₁'"| AND1
        NOT2[/¬/] -->|"S₀'"| AND1
        NOT3[/¬/] -->|"S₁'"| AND2
        NOT4[/¬/] -->|"S₀'"| AND3
    end

    subgraph AND Gates
        AND1["AND"] -->|"Y₀"| OR1
        AND2["AND"] -->|"Y₁"| OR1
        AND3["AND"] -->|"Y₂"| OR1
        AND4["AND"] -->|"Y₃"| OR1
    end

    subgraph Connections
        S1 --> NOT1
        S1 --> NOT4
        S0 --> NOT2
        S0 --> NOT3
        I0 --> AND1
        I1 --> AND2
        I2 --> AND3
        I3 --> AND4
        S1' --> AND2
        S1' --> AND3
        S0' --> AND1
        S0' --> AND4
        S0 --> AND2
        S1 --> AND4
    end

    OR1["OR"] --> Y["Y"]

Simplified Implementation Using ICs

A 4×1 MUX can also be implemented using IC 74153 (dual 4×1 MUX) or IC 74157 (quad 2×1 MUX in a single package). The IC 74153 contains two independent 4×1 MUXes, each with four data inputs, two select lines, and one output.

Truth Table Verification

The truth table confirms that the output $Y$ correctly selects one of the four inputs based on the select lines $S_1$ and $S_0$.

Final Answer: The 4×1 Multiplexer is designed using AND, OR, and NOT gates to select one of four inputs based on two select lines. The logic expression is derived from the truth table, and the circuit can be implemented using standard ICs like 74153. The output $Y$ is given by:

$$Y=\overline{S_1}\cdot \overline{S_0}\cdot I_0+\overline{S_1}\cdot S_0\cdot I_1+S_1\cdot \overline{S_0}\cdot I_2+S_1\cdot S_0\cdot I_3$$