Design a 2 bit asynchronous binary counter using T flip flop. Draw its timing diagram.

An asynchronous (ripple) counter is one where only the first flip-flop gets the external clock; each later flip-flop is clocked by the output of the one before it.

Design

• Use two T flip-flops, FF₀ (LSB, Q₀) and FF₁ (MSB, Q₁).
• Connect T = 1 on both, so each flip-flop toggles on every active clock edge.
• The external clock drives FF₀. Q₀ drives the clock of FF₁.
• With negative-edge-triggered flip-flops, FF₁ toggles every time Q₀ goes from 1 to 0.

        1          1
        |          |
      +-T-+      +-T-+
CLK --|>  |--Q0--|>  |--Q1
      +---+      +---+
       FF0        FF1

Count sequence

Timing diagram (negative-edge triggered)

CLK  _|‾|_|‾|_|‾|_|‾|_|‾|_
Q0   ___|‾‾‾|___|‾‾‾|___
Q1   _______|‾‾‾‾‾‾‾|___

Q₀ changes on every falling edge of CLK, so its frequency is half the clock frequency. Q₁ changes on every falling edge of Q₀, so its frequency is a quarter of the clock frequency. It counts 0 → 1 → 2 → 3 → 0 (mod-4 counter). The small delay of each flip-flop adds up down the chain, which is why it is called a ripple counter.