CSC116 Digital Logic

Digital LogicTU Board 2080

Implement the Boolean function F(P,Q,R,S) = ∑ (3,4,6,8,9,14) using: a) 8 to 1 multiplexer b) PLA c) Decoder

10

Implement the Boolean function F(P,Q,R,S) = ∑ (3,4,6,8,9,14) using:

  • a) 8 to 1 multiplexer

  • b) PLA

  • c) Decoder

Answer

F(P, Q, R, S) = Σm(3, 4, 6, 8, 9, 14)

a) Using an 8-to-1 multiplexer

Use P, Q, R as the select lines (S₂S₁S₀) and feed the data inputs with 0, 1, S or S′. For each combination of PQR, look at the two minterms that differ only in S:

PQR Minterms (S = 0, S = 1) In F? Data input
000 m0, m1 none I₀ = 0
001 m2, m3 m3 (S = 1) I₁ = S
010 m4, m5 m4 (S = 0) I₂ = S′
011 m6, m7 m6 (S = 0) I₃ = S′
100 m8, m9 both I₄ = 1
101 m10, m11 none I₅ = 0
110 m12, m13 none I₆ = 0
111 m14, m15 m14 (S = 0) I₇ = S′

So connect I₀ = 0, I₁ = S, I₂ = S′, I₃ = S′, I₄ = 1, I₅ = 0, I₆ = 0, I₇ = S′, with P, Q, R on the select lines. The MUX output is F.

b) Using a PLA

First minimise F with a K-map:

  • m8, m9 → P Q′ R′
  • m4, m6 → P′ Q S′
  • m6, m14 → Q R S′
  • m3 has no adjacent 1 → P′ Q′ R S

F = PQ′R′ + P′QS′ + QRS′ + P′Q′RS

PLA programming table (1 = true input, 0 = complemented input, – = not used):

Product term P Q R S Output F
PQ′R′ 1 0 0 – 1
P′QS′ 0 1 – 0 1
QRS′ – 1 1 0 1
P′Q′RS 0 0 1 1 1

The AND array makes the four product terms and the OR array adds them to give F.

c) Using a decoder

A 4-to-16 decoder with inputs P, Q, R, S (P as MSB) produces every minterm D₀ to D₁₅ on its outputs. Feed the outputs of the minterms in F into one OR gate:

F = D₃ + D₄ + D₆ + D₈ + D₉ + D₁₄

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