Explain instruction cycle, machine cycle and T states. Draw timing diagram of instruction cycle of STA instruction with brief description.

• Instruction cycle: the total time needed to fetch, decode and execute one complete instruction. It is made up of one or more machine cycles.
• Machine cycle: the time needed for one basic operation that accesses memory or I/O, such as opcode fetch, memory read, memory write, I/O read or I/O write. Each machine cycle takes 3 to 6 T-states.
• T-state: one clock period, the smallest unit of time in the microprocessor. At 3 MHz, one T-state is about 333 ns.

STA instruction (e.g. STA 2050H)

STA stores the accumulator in the memory address given in the instruction. It is a 3-byte instruction: opcode 32H, then the low address byte (50H), then the high address byte (20H).

It needs 4 machine cycles and 13 T-states:

Timing diagram (description)

        |<--- M1 opcode fetch --->|<- M2 read ->|<- M3 read ->|<- M4 write ->|
T-state   T1   T2   T3   T4        T1  T2  T3    T1  T2  T3    T1  T2  T3
A15-A8   PCH ............         PCH ........  PCH ........  20H .........
AD7-AD0  PCL | opcode 32H         PCL | 50H     PCL | 20H     50H | A data
ALE      ‾‾|_______               ‾‾|______     ‾‾|______     ‾‾|_______
IO/M'    ____ low (memory) for all cycles __________________________________
S1,S0    1,1 (fetch)               1,0 (read)    1,0 (read)    0,1 (write)
RD'      ‾‾‾|____|‾‾‾              ‾|____|‾      ‾|____|‾      ‾‾‾‾‾‾‾‾‾‾‾‾
WR'      ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾   ‾|____|‾

• In T1 of each cycle the address goes out, and ALE is high so the lower address byte on AD₇–AD₀ is latched.
• In T2–T3 the multiplexed bus carries data: RD′ goes low for the reads in M1–M3, and WR′ goes low in M4 to write the accumulator.
• In M1, T4 is used to decode the opcode.