PLDs: PLA, PAL, FPGAs – Architecture, Design & Applications

TAKEAWAYS:

• PLA and PAL are mask-programmable PLDs with fixed AND/OR arrays, while FPGAs are reconfigurable with logic blocks and interconnects.
• PLA has fully programmable AND and OR arrays, while PAL has a fixed OR array and programmable AND array.
• FPGAs use CLBs (Configurable Logic Blocks), routing matrices, and memory blocks for flexible logic implementation.
• Applications: PLA/PAL in telecom switches, FPGAs in high-speed networking (Ncell routers), and AI accelerators (Google TPUs).
• Design flow: Logic minimization → PLD programming → Verification (simulation, synthesis).
• Exam focus: Compare PLA vs. PAL, FPGA architecture, and state encoding for FSMs in PLDs.

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1. Introduction to Programmable Logic Devices (PLDs)

PLDs are integrated circuits designed to implement custom digital logic without hardwiring. They replace discrete logic gates or SSIs/MSIs (Small/Medium-Scale Integration) by providing programmable arrays of logic gates. PLDs are classified into:

• Mask-programmable (one-time programmable, e.g., PLA, PAL).
• Field-programmable (reconfigurable, e.g., FPGAs, CPLDs).

Why Use PLDs?

• Cost-effective for low-to-medium volume production.
• Faster prototyping than ASICs (Application-Specific ICs).
• Flexibility to update logic without redesigning hardware.

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2. PLA (Programmable Logic Array)

Definition & Architecture

A PLA consists of:

1. Programmable AND array (generates minterms).
2. Programmable OR array (combines minterms to form sum-of-products (SOP)).
3. Output stage (buffers or registers for sequential logic).

How PLA Works

• AND array: Each input line can be connected or disconnected to generate product terms.
• OR array: Each product term can be included or excluded in the final output.
• Example: Implementing $F=\overline{A}B+A\overline{B}$ (XOR gate).

Advantages & Disadvantages

Real-World Example: eSewa Payment Gateway

• PLA/PAL chips are used in hardware security modules (HSMs) to validate OTP (One-Time Password) logic.
• The AND/OR arrays encode cryptographic functions (e.g., SHA-256 hashing) for transaction verification.
• Why PLA? Fixed logic for high-speed validation without software delays.

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3. PAL (Programmable Array Logic)

Definition & Architecture

A PAL is similar to PLA but with:

• Fixed OR array (only programmable AND array).
• Outputs can be combinational or registered (for sequential logic).

Types of PALs

Worked Example: Traffic Light Controller (NTC)

Problem: Design a PAL to control traffic lights with 3 states (Red, Yellow, Green) based on sensor inputs (car presence). Solution:

1. Inputs: Sensor1, Sensor2, Timer.
2. Outputs: Red, Yellow, Green.
3. Logic:
   • If Sensor1 = 1 (car detected), set Green = 1 for Sensor1 lane.
   • Use registered outputs to store state for timing.

PAL Programming:

• AND array: Generate minterms like Sensor1·Timer.
• OR array: Combine to produce Green = Sensor1·Timer + Sensor2·¬Timer.

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4. FPGA (Field-Programmable Gate Array)

Definition & Architecture

An FPGA is a reconfigurable PLD with:

• Configurable Logic Blocks (CLBs): Contain LUTs (Look-Up Tables) and flip-flops.
• Routing matrices: Interconnect CLBs.
• I/O blocks: Interface with external signals.
• Memory blocks (BRAM): For storage.

How FPGAs Work

1. Design Entry: VHDL/Verilog code describes logic.
2. Synthesis: Logic is converted to netlist (gates and connections).
3. Place & Route: Netlist is mapped to CLBs and routing.
4. Configuration: FPGA is programmed via JTAG or configuration memory.

Advantages & Disadvantages

Real-World Example: Ncell 5G Base Stations

• FPGAs are used for real-time signal processing in 5G modems.
• Why FPGA?
  • Reconfigurable to adapt to new modulation schemes (e.g., 5G NR).
  • Parallel processing for beamforming (directing signals to users).
  • Low-latency routing for voice/data traffic.

Worked Example: Daraz Order Queue System (Simplified)

• Problem: Model a priority queue for orders using an FPGA.
• Solution:
  • Use CLBs to implement a priority encoder.
  • Flip-flops store order IDs.
  • LUTs determine priority based on order time and customer tier.

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5. Comparison: PLA vs. PAL vs. FPGA

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6. Design Flow for PLDs

1. Logic Design: Write Boolean equations or state diagrams.
2. Minimization: Use Karnaugh maps or Quine-McCluskey to reduce terms.
3. PLD Selection:
   • Use PLA for fully custom logic.
   • Use PAL for registered outputs.
   • Use FPGA for reconfigurable systems.
4. Programming:
   • PLA/PAL: Use JEDEC files (fuse programming).
   • FPGA: Use VHDL/Verilog → synthesis tools (Xilinx Vivado, Intel Quartus).
5. Verification:
   • Simulation (ModelSim, ISim).
   • Prototyping (FPGA development boards).

Example: WhatsApp Message Encryption (Simplified)

• PLA/PAL could encode AES (Advanced Encryption Standard) for low-power devices.
• FPGA is used in data centers for real-time encryption/decryption of messages.
• Why FPGA?
  • Parallel AES cores for high throughput.
  • Reconfigurable to update encryption standards.

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7. Fault Detection in PLDs

PLDs can have programming errors or hardware faults. Common techniques:

• Built-in Self-Test (BIST): Tests logic after programming.
• Redundancy: Duplicate critical paths in FPGAs.
• Configuration Verification: Checksums for FPGA bitstreams.

Example: Kathmandu Traffic Light Failure

• PLA/PAL in traffic controllers may fail due to power surges.
• Solution: Use watchdog timers (implemented in FPGA) to reset logic if stuck.

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In the Real World

1. eSewa & Khalti (Nepal)

   • PLA/PAL chips are used in hardware security modules (HSMs) to validate OTP logic for payments.
   • How? The AND/OR arrays encode cryptographic hashing (e.g., SHA-256) to verify user inputs before processing transactions.

2. Ncell 5G Network

   • FPGAs handle real-time signal processing in 5G base stations.
   • How? The CLBs implement OFDM (Orthogonal Frequency-Division Multiplexing) for high-speed data transmission, while BRAM stores user profiles for dynamic routing.

3. Daraz & Pathao (Logistics)

   • FPGAs optimize order routing in delivery systems.
   • How? A priority encoder (CLB-based) selects the nearest delivery agent based on GPS data and traffic conditions, reducing delivery time.

4. Nepal Stock Exchange (NEPSE)

   • PALs are used in trading terminals to validate buy/sell orders in microseconds.
   • How? The registered outputs store order queues, and the fixed OR array ensures FIFO (First-In-First-Out) processing to prevent fraud.

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Exam Tip

What Examiners Look For

1. Definitions & Differences:

   • Clearly distinguish PLA (fully programmable) vs. PAL (fixed OR array).
   • Explain FPGA reconfigurability vs. PLA/PAL one-time programming.

2. Architecture Diagrams:

   • Draw AND/OR arrays for PLA/PAL.
   • Label CLBs, routing matrices, and I/O blocks for FPGAs.

3. Worked Examples:

   • PLA/PAL: Implement a traffic light controller or simple FSM.
   • FPGA: Describe how a priority encoder or AES core is mapped to CLBs.

4. Applications:

   • Link PLA/PAL to telecom/banking (eSewa, banks).
   • Link FPGAs to high-speed networks (Ncell, Google TPUs).

5. Common Pitfalls:

   • Don’t confuse PLA and PAL (PAL has fixed OR array!).
   • Don’t forget registered outputs in PALs for sequential logic.
   • FPGAs are not ASICs—they have configurable delays and power overhead.

Model Answer Structure for Exam Questions

Question: "List out the differences between PAL and PLA." Answer:

Question: "Write short notes on FPGA." Answer: An FPGA (Field-Programmable Gate Array) is a reconfigurable PLD consisting of:

• CLBs (Configurable Logic Blocks): Contain LUTs and flip-flops.
• Routing matrices: Interconnect CLBs dynamically.
• I/O blocks: Interface with external signals. Applications: Used in 5G modems (Ncell), AI accelerators (Google TPUs), and real-time signal processing. Advantages: Reprogrammable, high performance; Disadvantages: Higher cost, power consumption.

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Final Checklist Before Exam

✅ Can you draw the architecture of PLA, PAL, and FPGA? ✅ Can you compare PLA vs. PAL vs. FPGA in a table? ✅ Can you implement a simple logic function (e.g., XOR) in PLA/PAL? ✅ Can you explain how FPGAs are used in Ncell 5G or eSewa HSMs? ✅ Do you know the design flow (minimization → programming → verification)?