Sequential Circuits: Flip-Flops, Registers & Timing Essentials

Sequential Circuits: Memory in Action

Sequential circuits differ from combinational circuits by remembering past inputs via storage elements (flip-flops). Their behavior depends on clock signals and state transitions, making them essential for registers, counters, and memory units. This unit decodes how flip-flops work, how to design registers, and how timing affects reliability.

1. Flip-Flops: The Building Blocks of Memory

Flip-flops are binary storage elements that hold a single bit (0 or 1) until instructed to change. They are the backbone of sequential circuits, enabling systems to "remember" previous states.

Types of Flip-Flops

Flip-flops are classified by:

• Input logic (SR, D, JK, T)
• Triggering mode (level-triggered vs. edge-triggered)

1.1 SR Flip-Flop (Set-Reset)

The simplest flip-flop, with two inputs: S (Set) and R (Reset).

• Operation:
  • S=1, R=0 → Output Q=1 (Set)
  • S=0, R=1 → Output Q=0 (Reset)
  • S=1, R=1 → Forbidden state (output undefined)
  • S=0, R=0 → Holds previous state (memory function)

Real Picture: IMAGE: SR latch circuit diagram with NOR gates | A basic SR latch using two cross-coupled NOR gates.

Problem: The forbidden state (S=R=1) makes SR flip-flops unreliable for most applications. This led to the development of D, JK, and T flip-flops.

1.2 D Flip-Flop (Data/Delay)

• Single data input (D) and a clock (CLK).
• Output Q follows D only on the clock edge (edge-triggered).
• No forbidden state: D=0 → Q=0, D=1 → Q=1.

Truth Table:

Why D Flip-Flops?

• Simpler than SR or JK (only one input).
• Used in registers, shift registers, and memory units.

Example: In eSewa, when you confirm a transaction, the system uses D flip-flops to lock the transaction ID until the payment is processed.

1.3 JK Flip-Flop (Universal Flip-Flop)

• Inputs: J (Set), K (Reset), CLK.
• No forbidden state: J=K=1 → Toggles (output flips).
• Can replace SR and D flip-flops (universal).

Truth Table:

Excitation Table (for JK → D conversion):

Real Picture: IMAGE: 74LS76 JK flip-flop IC pinout | The 74LS76 JK flip-flop IC, used in counters and memory.

1.4 T Flip-Flop (Toggle)

• Single input (T): If T=1, output toggles; if T=0, output holds.
• Used in counters and dividers.

Truth Table:

Derivation from JK:

• Connect J=K=T to a JK flip-flop.

2. Triggering Modes: Level vs. Edge

Flip-flops can be level-triggered or edge-triggered, affecting their timing behavior.

2.1 Level-Triggered Flip-Flops

• Changes state when clock is HIGH or LOW (e.g., SR latch).
• Problem: Race conditions (output depends on input setup time).
• Example: If CLK=1 and D changes during CLK=1, output may glitch.

2.2 Edge-Triggered Flip-Flops

• Changes state only at the clock edge (rising/falling).
• More reliable: No race conditions if setup/hold times are met.
• Types:
  • Positive edge-triggered (rising edge, ↑).
  • Negative edge-triggered (falling edge, ↓).

Timing Diagram Comparison:

Exam Tip: Always assume edge-triggered unless specified otherwise.

3. Registers: Storing Multi-Bit Data

A register is a group of flip-flops that stores n bits (e.g., 8-bit, 16-bit). Used in:

• CPU registers (accumulator, program counter).
• Memory addresses.
• Data buses.

3.1 Basic Register Design

• D Flip-Flops in parallel (each bit stored in a separate flip-flop).
• Common clock signal for synchronization.

Example: An 8-bit register uses 8 D flip-flops:

D7 D6 D5 D4 D3 D2 D1 D0
  |   |   |   |   |   |   |
  Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Mermaid Block Diagram:

flowchart LR
    CLK --> DFF1["DFF Q0"]
    CLK --> DFF2["DFF Q1"]
    CLK --> DFF3["DFF Q2"]
    CLK --> DFF4["DFF Q3"]
    CLK --> DFF5["DFF Q4"]
    CLK --> DFF6["DFF Q5"]
    CLK --> DFF7["DFF Q6"]
    CLK --> DFF8["DFF Q7"]
    DFF1 -->|"Q0"| OUT0
    DFF2 -->|"Q1"| OUT1
    DFF3 -->|"Q2"| OUT2
    DFF4 -->|"Q3"| OUT3
    DFF5 -->|"Q4"| OUT4
    DFF6 -->|"Q5"| OUT5
    DFF7 -->|"Q6"| OUT6
    DFF8 -->|"Q7"| OUT7

3.2 Shift Registers

• Serial-in, parallel-out (SIPO) or parallel-in, serial-out (PISO).
• Used in data transmission (UART), memory testing.

Example: A 4-bit shift register (using D flip-flops):

D0 ---> Q0 ---> D1 ---> Q1 ---> D2 ---> Q2 ---> D3 ---> Q3

Mermaid Shift Register:

flowchart LR
    D0["D0"] -->|"CLK"| Q0["Q0"]
    Q0 --> D1["D1"]
    D1 -->|"CLK"| Q1["Q1"]
    Q1 --> D2["D2"]
    D2 -->|"CLK"| Q2["Q2"]
    Q2 --> D3["D3"]
    D3 -->|"CLK"| Q3["Q3"]

Real-World Use:

• Ncell’s billing system uses shift registers to process call duration data in serial form before storing it in memory.

4. Timing Analysis: Setup and Hold Times

Flip-flops require setup time (tₛ) and hold time (tₕ) to avoid metastability (invalid output).

4.1 Critical Timing Parameters

Timing Diagram for Safe Operation: Violation Example (Setup Time Violation): → Glitch or wrong output if D changes too late before CLK edge.

5. Direct Command Flip-Flops

These flip-flops have asynchronous inputs (Set/Reset) that override the clock.

• Asynchronous Clear (AC) or Asynchronous Preset (AP).
• Used for immediate reset (e.g., power-on reset).

Example: A D flip-flop with async clear:

D ---> Q
|     |
CLK  AC (Active LOW)

• If AC=0, Q=0 immediately, regardless of CLK.

Real Picture: IMAGE: 74LS74 D flip-flop with async clear pinout | The 74LS74 IC with CLR (asynchronous clear).

In the Real World

1. eSewa Transactions

   • When you pay a bill, eSewa uses D flip-flops to lock the transaction ID in memory until the payment is confirmed. This prevents duplicate processing.
   • Registers store your account details securely during the transaction.

2. Ncell Billing System

   • Ncell’s system uses shift registers to serialize call duration data before storing it in databases. This reduces memory access time.
   • JK flip-flops in counters track call minutes for billing.

3. Bank Loan Interest Calculation (Nepal Bank Limited)

   • Banks use sequential circuits (counters) to calculate compound interest over months. A 4-bit counter could track years (0-15), while flip-flops store intermediate interest values.
   • Example: If a loan has a 5% annual interest, a counter increments yearly, and flip-flops store the accumulated interest.

Exam Tip: What to Focus On

1. Flip-Flop Types:

   • Know the truth tables for SR, D, JK, and T flip-flops.
   • Derive one from another (e.g., JK → D conversion).

2. Triggering Modes:

   • Edge-triggered is default unless stated. Level-triggered causes race conditions.

3. Registers:

   • Parallel vs. serial operation.
   • Shift registers for data transmission.

4. Timing Diagrams:

   • Setup/hold time violations lead to wrong outputs. Always check timing in exam problems.

5. Real-World Applications:

   • eSewa, Ncell, banks use flip-flops/registers for data storage, counters, and synchronization.

6. Common Mistakes:

   • Forgetting forbidden states in SR flip-flops.
   • Misinterpreting positive vs. negative edge-triggered.
   • Ignoring asynchronous inputs (clear/preset).

Final Note: Sequential circuits are the heart of digital systems. Master flip-flops, registers, and timing to ace the exam—and understand how your phone, bank, and e-commerce apps work under the hood!