8086 Architecture & Instruction Set: Core Features, Flags & ALP

TAKEAWAYS:

• The 8086 is a 16-bit microprocessor with a 16-bit data bus and 20-bit address bus, enabling access to 1 MB of memory (2²⁰ = 1,048,576 bytes).
• It splits work between the Bus Interface Unit (BIU) (handles memory/IO access) and Execution Unit (EU) (executes instructions), allowing pipelined operation for faster performance.
• 14 flags (e.g., SF, ZF, CF, OF) track arithmetic/logic results, enabling conditional jumps and loops in assembly programs.
• Instructions are 1–6 bytes long and execute in 1–5 clock cycles (e.g., MOV takes 1 cycle; MUL takes 70–82 cycles).
• The instruction set is divided into 5 groups: data transfer, arithmetic, logical, control transfer, and string manipulation.
• Real-world use: Banks use 8086-like processors in ATMs for transaction validation; industrial PLCs (Programmable Logic Controllers) rely on 8086 assembly for real-time control.

1. 8086 Microprocessor Architecture: The Core Design

The 8086 is the first 16-bit microprocessor from Intel, introduced in 1978. It revolutionized computing by replacing the 8-bit 8085 and enabling faster, more complex applications. Below is its internal architecture, split into two key units:

1.1 Block Diagram of 8086

Key Components:

1.2 How the 8086 Works: Pipelining

The 8086 uses pipelining to overlap instruction fetching and execution:

1. BIU fetches the next instruction while the EU executes the current one.
2. If the BIU is busy (e.g., waiting for memory), the EU stalls until data is ready.
3. This design reduces idle time compared to the 8085 (which fetches and executes sequentially).

Example:

• While the EU is executing ADD AX, BX, the BIU fetches the next instruction (MOV CX, DX).
• If the next instruction is in a different memory segment, the BIU must wait for the segment register to be loaded.

1.3 Memory Organization: Segments and Offsets

The 8086 has a 20-bit address bus but only 16-bit registers, so it uses segmented memory:

• Physical Address = Segment Register × 16 + Offset (e.g., CS:IP for code segment, DS:SI for data segment).
• Maximum addressable memory = 1 MB (2²⁰ bytes).

Example Calculation: If CS = 2000H and IP = 0050H, the physical address is:

2000H × 16 + 0050H = 20000H + 0050H = 20050H

2. The 8086 Flag Register: Status and Control Bits

The 16-bit Flag Register tracks the result of arithmetic/logic operations and controls processor behavior. It has 9 flags, but only 6 are user-modifiable (the rest are system flags).

2.1 Flag Register Layout

2.2 Key Flags Explained

Example: How Flags Change

MOV AL, 50H    ; AL = 0101 0000
MOV BL, 30H    ; BL = 0011 0000
ADD AL, BL     ; AL = 0101 0000 + 0011 0000 = 1000 0000 (80H)

• SF = 1 (result is negative in signed interpretation).
• ZF = 0 (result is not zero).
• CF = 1 (unsigned overflow, since 50H + 30H = 80H > 255).
• OF = 0 (no signed overflow, since 80H is within -32768 to 32767).

3. 8086 Instruction Set: Groups and Examples

The 8086 instruction set is divided into 5 groups:

3.1 Data Transfer Instructions

Move data between registers, memory, and I/O ports. Examples:

Worked Example: Bank ATM Transaction Validation An ATM uses 8086 assembly to validate a PIN. Suppose:

• The PIN is stored in memory at 2000H.
• The user enters a PIN in AL.
• The ATM compares and sets flags accordingly.

MOV AL, [2000H]   ; Load correct PIN into AL
CMP AL, 48H       ; Compare with user input (48H = '0')
JZ  VALID         ; Jump if ZF=1 (PIN correct)
JMP INVALID       ; Else, jump to error
VALID: MOV AH, 01H ; Set success flag
INVALID: HLT      ; Halt

• If CMP sets ZF=1, the PIN is correct (JZ jumps).
• If ZF=0, the PIN is wrong (JMP skips validation).

3.2 Arithmetic Instructions

Perform addition, subtraction, multiplication, and division. Examples:

Worked Example: Daraz Order Queue Processing Daraz’s backend uses 8086-like logic to manage order queues. Suppose:

• CX holds the number of pending orders.
• AX holds the current order ID.
• Each order processing decrements CX.

MOV CX, 10       ; 10 pending orders
PROCESS_LOOP:
    CALL PROCESS_ORDER  ; Simulate processing
    LOOP PROCESS_LOOP   ; Decrement CX, jump if CX ≠ 0
    HLT                ; All orders processed

• LOOP uses CX as a counter and jumps if CX ≠ 0.

3.3 Logical Instructions

Perform bitwise operations (AND, OR, NOT, XOR, SHIFT). Examples:

Worked Example: NTC Traffic Light Control NTC uses logical operations to control traffic lights. Suppose:

• AL holds the current light state (00000001 = Red, 00000010 = Green).
• We want to toggle Green to Yellow (00000010 → 00000100).

MOV AL, 02H       ; Green light (00000010)
SHL AL, 1         ; Shift left: 00000100 (Yellow)
OUT 70H, AL       ; Send to traffic light controller

3.4 Control Transfer Instructions

Change the flow of execution (JMP, CALL, RET, LOOP). Examples:

Worked Example: Pathao Ride Validation Pathao’s backend validates ride requests. Suppose:

• AX holds the ride status (0 = valid, 1 = invalid).
• We jump to APPROVE if valid, else REJECT.

CMP AX, 0         ; Check ride status
JZ  APPROVE       ; If ZF=1 (AX=0), approve
JMP REJECT        ; Else, reject
APPROVE: MOV BL, 1 ; Set approval flag
REJECT: HLT

3.5 String Instructions

Process strings (MOVSB, CMPSB, SCAS, LODSB). Examples:

Worked Example: WhatsApp Message Encryption WhatsApp uses string operations to process messages. Suppose:

• SI points to plaintext.
• DI points to ciphertext.
• We copy and encrypt each byte.

MOV SI, PLAINTEXT  ; Source index
MOV DI, CIPHERTEXT ; Destination index
MOV CX, 100        ; 100 bytes to process
ENCRYPT_LOOP:
    LODSB           ; Load byte from [SI] to AL
    XOR AL, 55H     ; Simple XOR encryption
    STOSB           ; Store to [DI]
    LOOP ENCRYPT_LOOP

4. Instruction Execution: Clock Cycles and Timing

Each 8086 instruction takes 1–5 clock cycles to execute, depending on:

1. Instruction type (e.g., MOV takes 1 cycle; MUL takes 70–82 cycles).
2. Memory access (if the instruction requires fetching data from memory).
3. Pipelining (BIU/EU overlap).

4.1 Timing Diagram for ADD M (Add Memory)

sequenceDiagram
    participant BIU
    participant EU
    participant Memory
    BIU->>Memory: Fetch Instruction (ADD M)
    Memory-->>BIU: Return ADD M
    BIU->>EU: Pass Instruction
    EU->>Memory: Fetch Operand (M)
    Memory-->>EU: Return Operand
    EU->>EU: Perform ADD
    EU->>Memory: Write Result (if needed)
    EU->>BIU: Signal Completion
    note right: Total Time: 13 T-states (5 clock cycles for 3 MHz)

Calculation for ADD M at 3 MHz:

• T-states for ADD M: 13 (5 clock cycles).
• Clock period (T) = 1/frequency = 1/3MHz ≈ 0.333 μs.
• Total time = 13 × 0.333 μs ≈ 4.33 μs.

4.2 Instruction Length and Execution Time

5. 8086 vs. 8085: Key Differences

Why 8086 is Better:

• 16-bit design allows larger data and faster processing.
• Pipelining reduces idle time.
• Segmented memory enables larger programs.
• More instructions support complex tasks.

6. Real-World Applications of 8086 Architecture

The 8086’s design principles are still used in modern embedded systems, industrial controls, and legacy software.

6.1 eSewa Payment Validation

eSewa’s backend uses 8086-like logic for transaction validation:

• Flags check if a transaction is approved (ZF=1 for success).
• Arithmetic instructions calculate fees and balances.
• Control transfers (JMP, CALL) handle error cases.

Example:

MOV AX, [BALANCE]  ; Load user balance
CMP AX, [AMOUNT]   ; Compare with transaction amount
JAE APPROVE        ; If AX ≥ AMOUNT, approve (no overflow)
JMP DECLINE        ; Else, decline

6.2 Ncell Tower Signal Strength Monitoring

Ncell uses 8086 assembly in base stations to:

• Logical operations (AND, OR) filter signal data.
• Loops (LOOP) process multiple towers.
• I/O instructions (IN, OUT) read sensor data.

Example:

MOV SI, TOWER_DATA ; Point to signal data
MOV CX, 10         ; 10 towers
CHECK_SIGNAL:
    LODSB           ; Load signal strength
    CMP AL, 50H      ; Compare with threshold (80H)
    JAE LOG_ERROR    ; If signal weak, log error
    LOOP CHECK_SIGNAL

6.3 Industrial PLCs (Programmable Logic Controllers)

Factories use 8086-based PLCs to control machinery:

• Timing instructions (HLT, WAIT) synchronize motors.
• String operations process sensor inputs.
• Interrupts handle emergencies.

Example:

WAIT               ; Wait for sensor input
IN AL, 80H         ; Read temperature sensor
CMP AL, 90H        ; Compare with threshold
JAE SHUTDOWN       ; If too hot, shutdown

Exam Tip: How to Score Full Marks

1. Draw and Label Diagrams:

   • Always draw the 8086 block diagram with BIU/EU labeled.
   • Show flag register bits with their names and functions.
   • For timing diagrams, label T-states and clock cycles.

2. Explain with Examples:

   • When asked about flags, show how they change in an arithmetic operation.
   • For instructions, write a short ALP snippet (3–4 lines) to demonstrate.

3. Compare 8086 vs. 8085:

   • Use a table to highlight key differences (data bus, memory, pipelining).

4. Calculate Execution Time:

   • For timing questions, convert frequency to period and multiply by T-states.
   • Example: At 2 kHz, T = 1/2000 = 0.5 ms. For LDA 2000H (13 T-states), time = 13 × 0.5 ms = 6.5 ms.

5. Real-World Applications:

   • Relate flags to banking (transaction success/failure).
   • Use loops for Daraz order processing.
   • Apply I/O instructions to NTC traffic lights.

6. Avoid Common Mistakes:

   • Don’t confuse 8085 (8-bit) with 8086 (16-bit).
   • Remember: Physical Address = Segment × 16 + Offset.
   • For MUL/DIV, note they take many cycles (70–82 for MUL).

Final Checklist Before Exam: ✅ Can you draw the 8086 block diagram? ✅ Do you know all 6 user-modifiable flags and when they set? ✅ Can you write a 4-line ALP for a given task (e.g., find max of two numbers)? ✅ Do you know how to calculate execution time for any instruction? ✅ Can you compare 8086 and 8085 in a table?