Arithmetic Circuits & Complements: Adders, Subtractors, Complements & Floating Point

TAKEAWAYS:

• Adders/subtractors are the building blocks of CPU arithmetic units, enabling binary addition/subtraction via logic gates (e.g., half/full adders, ripple/carry-lookahead adders).
• Complements (1’s/2’s) simplify subtraction by converting it into addition, critical for signed number operations and overflow detection in processors.
• Floating-point representation (IEEE 754) standardizes how computers store real numbers, used in scientific apps (e.g., weather modeling) and graphics (e.g., game engines).
• Error detection (parity bits) ensures data integrity in transmissions (e.g., WhatsApp message checks) and memory storage.
• Subtraction methods (direct, 1’s complement, 2’s complement) trade off hardware complexity vs. speed—2’s complement is dominant in modern CPUs.
• Real-world ties: Banks use 2’s complement for loan interest calculations; eSewa/Khalti apply parity bits to secure transactions; NTC’s billing systems rely on floating-point for precise energy unit conversions.

1. Arithmetic Circuits: The Heart of CPU Math

Computers perform arithmetic using combinational logic circuits—circuits whose outputs depend only on current inputs (no memory). The two fundamental operations are addition and subtraction, implemented via adders and subtractors.

1.1 Half Adder: The Simplest Adder

A half adder adds two single-bit inputs (A and B) and produces:

• Sum (S) = A ⊕ B (XOR)
• Carry (C_out) = A · B (AND)

Why? Addition rules:

• 0 + 0 = 0 (no carry)
• 0 + 1 = 1 (no carry)
• 1 + 0 = 1 (no carry)
• 1 + 1 = 0 (carry = 1)

flowchart LR
    A["A"] --> XOR["A ⊕ B"] --> S["Sum (S)"]
    A --> AND["A · B"] --> C["Carry (C_out)"]
    B["B"] --> XOR
    B --> AND

Limitations: Cannot handle carry-in from previous additions (used for multi-bit numbers).

1.2 Full Adder: Adding with Carry

A full adder extends the half adder by adding a carry-in (C_in) and produces:

• Sum (S) = A ⊕ B ⊕ C_in
• Carry-out (C_out) = (A · B) + (B · C_in) + (A · C_in)

Truth Table:

Logic Diagram:

Real-World Use:

• eSewa/Khalti: When you transfer ₹500, the app uses a 4-bit ripple adder (chain of full adders) to add your balance and the transaction amount, propagating carries bit-by-bit.
• NTC Billing: Your electricity unit consumption is summed using adders in the smart meter’s microcontroller.

1.3 Ripple Carry Adder (RCA)

For multi-bit addition, we cascade full adders. The carry-out of one adder becomes the carry-in of the next.

Example: Add 1011 (11) and 0101 (5) using a 4-bit RCA.

   1 0 1 1   (11)
+  0 1 0 1   (5)
-----------
   1 0 0 0 0  (16)

Step-by-Step:

1. LSB (bit 0): 1 + 1 = 10 → S0 = 0, C1 = 1
2. Bit 1: 1 + 0 + C1(1) = 10 → S1 = 0, C2 = 1
3. Bit 2: 0 + 1 + C2(1) = 10 → S2 = 0, C3 = 1
4. MSB (bit 3): 1 + 0 + C3(1) = 10 → S3 = 0, C4 = 1 (overflow)

Problem: Carry propagation delay grows with bit-width (slow for 32/64-bit CPUs). Solution: Carry-Lookahead Adders (CLA) or Carry-Skip Adders (used in modern CPUs).

1.4 Subtraction Using Adders

Subtraction (A - B) can be done via:

1. Direct Subtraction: Use a subtractor circuit (like a full adder but with inverted inputs).
2. Complement Method: Convert subtraction to addition using 1’s/2’s complement.

Why? CPUs use 2’s complement for subtraction because:

• It’s faster (same hardware as addition).
• Handles negative numbers natively.

2. Number Complements: The Secret to Fast Subtraction

Complements simplify subtraction by converting it into addition.

2.1 1’s Complement

• Definition: Invert all bits of a number.
  • For N = nₖnₖ₋₁...n₀, 1’s complement = (1 - nₖ)(1 - nₖ₋₁)...(1 - n₀).
• Example: 1’s complement of 1011 (11) is 0100.

Subtraction Using 1’s Complement: A - B = A + (1’s complement of B) + 1 (end-around carry). Example: Subtract 5 (0101) from 11 (1011):

1. 1’s complement of 5 = 1010
2. Add 1011 + 1010 = 10101 (5 bits)
3. Add end-around carry 1 → 10110 → Discard overflow → 0110 (6).

Problem: Double representation of zero (0000 and 1111), causing ambiguity.

2.2 2’s Complement

• Definition: Add 1 to the least significant bit (LSB) of the 1’s complement.
  • 2’s complement = 1’s complement + 1.
• Example: 2’s complement of 1011 (11) is 0101 (-3 in 4-bit).

Subtraction Using 2’s Complement: A - B = A + (2’s complement of B). Example: Subtract 5 (0101) from 11 (1011):

1. 2’s complement of 5 = 1011 (invert 0101 → 1010 + 1 = 1011).
2. Add 1011 + 1011 = 10110 → Discard overflow → 0110 (6).

Advantages:

• Single representation of zero (0000).
• No end-around carry needed.
• Used in all modern CPUs (x86, ARM).

Real-World Use:

• Bank Loan Interest: If you borrow ₹10,000 at 10% interest, the bank’s system uses 2’s complement to calculate (10000 - (10000 * 0.10)) for repayment.
• NEPSE Stock Prices: When a stock drops from ₹500 to ₹450, the exchange’s backend uses 2’s complement arithmetic.

2.3 Comparison of Complement Methods

3. Subtraction Circuits

3.1 Half Subtractor

Subtracts B from A and produces:

• Difference (D) = A ⊕ B
• Borrow (B_out) = A' · B

Truth Table:

Logic Diagram:

3.2 Full Subtractor

Subtracts B from A with a borrow-in (B_in):

• Difference (D) = A ⊕ B ⊕ B_in
• Borrow-out (B_out) = (A' · B) + (A' · B_in) + (B · B_in)

Real-World Use:

• Pathao Fare Calculation: When you request a ride, the app’s backend uses a 4-bit subtractor to deduct the fare from your wallet balance.

4. Arithmetic Logic Unit (ALU): The Brain of the CPU

An ALU combines adders, subtractors, and logic gates to perform arithmetic and logical operations. It’s the core of every CPU.

Key Operations:

• Addition (A + B)
• Subtraction (A - B)
• Logical AND (A · B)
• Logical OR (A + B)
• XOR (A ⊕ B)

Block Diagram:

Real-World Use:

• Google Search: When ranking pages, Google’s servers use ALUs to perform billions of arithmetic operations per second for relevance scores.
• WhatsApp Encryption: The app’s end-to-end encryption relies on ALUs to compute hashes and digital signatures.

5. Floating-Point Representation: Storing Real Numbers

Computers store real numbers in floating-point format (IEEE 754 standard) to handle very large/small numbers efficiently.

5.1 IEEE 754 Single-Precision (32-bit)

Example: Store 6.75 in 32-bit floating-point.

1. Normalize: 6.75 = 1.01011 × 2² (binary 110.11).
2. Sign: 0 (positive).
3. Exponent: 2 + 127 = 129 (10000001 in binary).
4. Mantissa: 01011000000000000000000 (drop leading 1). Final: 0 10000001 01011000000000000000000

Real-World Use:

• YouTube Video Processing: When compressing video frames, YouTube’s servers use floating-point to store pixel brightness values (e.g., 127.5 for half-white).
• NTC Weather Data: Meteorological stations transmit temperature/humidity as floating-point numbers for analysis.

5.2 Floating-Point Operations

Addition/Subtraction:

1. Align exponents (shift mantissa).
2. Add/subtract mantissas.
3. Normalize result.
4. Round if needed.

Example: Add 1.0 × 2⁰ and 1.0 × 2¹:

1. Align: 1.0 × 2⁰ and 0.1 × 2¹.
2. Add: 1.1 × 2⁰.
3. Normalize: 1.1 × 2⁰ (no change).

Multiplication:

1. Multiply mantissas.
2. Add exponents.
3. Normalize.

Real-World Use:

• Daraz Discount Calculations: When applying a 20% discount, the system uses floating-point to compute (price × 0.80) precisely.

6. Error Detection: Parity Bits

Parity bit ensures data integrity by detecting single-bit errors during transmission/storage.

6.1 Even Parity

• Definition: Set parity bit to make total 1s even.
• Example: 1011 (3 1s) → Parity bit 1 → 11011 (4 1s).

6.2 Odd Parity

• Definition: Set parity bit to make total 1s odd.
• Example: 1011 (3 1s) → Parity bit 0 → 01011 (3 1s).

Real-World Use:

• WhatsApp Messages: When you send a message, WhatsApp adds a parity bit to detect corruption during transmission.
• Bank Transactions: Khalti uses parity bits to verify that your account number was transmitted correctly.

7. Worked Example: Design a 4-bit Adder-Subtractor

Problem: Design a circuit that adds or subtracts two 4-bit numbers based on a control signal M (M=0 for addition, M=1 for subtraction).

Solution:

1. For Addition (M=0):
   • Use a 4-bit ripple adder.
2. For Subtraction (M=1):
   • Use 2’s complement of B and add to A.
   • Invert B and add 1 (using XOR gates and a half adder).

Circuit:

Explanation:

• When M=1, B is inverted (2’s complement setup).
• A half adder adds 1 to the inverted B3 to complete 2’s complement.
• The ripple adder then performs A + (2’s comp B).

Real-World Tie:

• Ncell Billing: When your phone bill is ₹999 and you pay ₹1000, the system uses this adder-subtractor to compute (1000 - 999) = 1 (change).

8. Common Pitfalls and Exam Tips

Exam Tip 1: Master 2’s Complement Subtraction

• Always add 1 to the 1’s complement to get 2’s complement.
• Overflow: If the result has a leading 1 in the sign bit, it’s negative (e.g., 10110 in 5 bits is -6).
• Example: Subtract 7 (0111) from 3 (0011) in 4-bit:
  1. 2’s comp of 7 = 1001 (invert 0111 → 1000 + 1 = 1001).
  2. 0011 + 1001 = 1100 → Discard overflow → 100 (-4 in 3 bits, but actual result is -4 in 4-bit).

Exam Tip 2: Floating-Point Normalization

• Always normalize to 1.xxxx form before storing.
• Example: 0.0101 × 2³ → Normalize to 1.01 × 2¹.

Exam Tip 3: Parity Bit Questions

• Even/Odd: Check if the number of 1s is even/odd.
• Error Detection: If parity fails, a single bit flipped during transmission.

Exam Tip 4: Adder-Subtractor Design

• Use XOR gates to invert inputs for subtraction.
• Always show the control signal (M) in your diagram.

Exam Tip 5: K-Map Simplification for Adders

• Simplify adder expressions using K-maps before drawing circuits.
• Example: Simplify Sum = A ⊕ B ⊕ C_in (already minimal).

9. Summary Table: Key Circuits and Their Uses

10. Practice Problems for Exam Readiness

1. Design a 4-bit subtractor using full subtractors and show its truth table.
2. Convert 1101.101 to IEEE 754 single-precision floating-point.
3. Add 1011 and 0101 using 2’s complement and show all steps.
4. Design a circuit that adds two 4-bit numbers and outputs the result in 2’s complement if negative.
5. Explain how a parity bit detects a single-bit error in 110101 (even parity).

11. In the Real World

1. eSewa/Khalti Transactions:

   • Idea Used: 2’s complement arithmetic and ripple carry adders.
   • How: When you pay ₹500 for a bill, the app’s backend uses a 32-bit adder to update your balance:
     • Balance (A) = 10000 (₹10,000)
     • Transaction (B) = 500
     • 2’s comp of B = 11111111111111111111111111111010 (for 32-bit)
     • A + (2’s comp B) = 01001100010000000000000000001010 → New balance 9500.

2. NTC Smart Meters:

   • Idea Used: Full adders and floating-point.
   • How: Your electricity consumption (e.g., 25.75 units) is stored as a floating-point number. The meter’s microcontroller uses a 4-bit adder to accumulate usage every second.

3. Daraz Order Processing:

   • Idea Used: Priority encoders (from Unit 5) + subtractors.
   • How: When you order ₹899 worth of items, Daraz’s system:
     • Uses a subtractor to check stock: Stock - Order ≥ 0.
     • Uses parity bits to verify order confirmation messages.

4. NEPSE Stock Trading:

   • Idea Used: Floating-point arithmetic and 2’s complement.
   • How: When a stock price drops from ₹600 to ₹550:
     • The exchange’s system stores prices as floating-point (550.00).
     • Uses 2’s complement to compute 600 - 550 = 50 (price drop).

5. WhatsApp End-to-End Encryption:

   • Idea Used: Parity bits and ALUs.
   • How: When you send a message:
     • The app computes a parity bit for each byte.
     • The receiver checks parity to detect corruption during transmission.

12. Exam Tip: How to Score Full Marks

• For circuit design questions:

  • Show the truth table (mandatory).
  • Draw the logic diagram (use standard gate symbols).
  • Label all inputs/outputs clearly.
  • Explain the control signals (e.g., M for adder-subtractor).

• For complement/subtraction:

  • Write all steps (1’s complement → add 1 → add to minuend).
  • Show overflow handling (discard extra bit in 2’s complement).

• For floating-point:

  • Break into sign, exponent, mantissa.
  • Show normalization explicitly.
  • Mention IEEE 754 if asked for standard format.

• For error detection:

  • Define even/odd parity.
  • Show how a single-bit error is detected.

Final Note: This unit is heavily tested in TU exams. Focus on:

1. 2’s complement subtraction (most common question).
2. Adder/subtractor design (always show truth table + circuit).
3. Floating-point conversion (normalization is key).
4. Parity bit applications (real-world examples score extra marks).