Counters & Registers: Types, Design, State Machines & Applications

TAKEAWAYS

• Counters are sequential circuits that generate a sequence of binary states (e.g., MOD-N counters for modulo-N counting) and are classified as asynchronous (ripple) or synchronous based on clock propagation.
• Registers store binary data temporarily and can shift data serially (bit-by-bit) or in parallel (all bits at once), with applications in memory, I/O buffers, and arithmetic units.
• State diagrams and excitation tables are essential tools for designing counters/registers, linking flip-flop inputs to next-state transitions.
• JK/T flip-flops are preferred for counter design due to their simplicity in toggling states (e.g., a JK flip-flop with J=K=1 toggles on every clock pulse).
• Bidirectional shift registers and ring counters enable flexible data movement (left/right shifts) or circular data storage, critical for applications like data encryption or traffic light sequencing.
• Timing diagrams reveal critical race conditions in asynchronous counters (e.g., propagation delays in ripple counters) and must be analyzed for correct operation.

1. Introduction to Counters

A counter is a sequential circuit that stores and increments binary numbers in a predefined sequence. Counters are classified based on:

• Clocking mechanism: Asynchronous (ripple) vs. synchronous.
• Counting direction: Up, down, or bidirectional.
• Modulo operation: MOD-N counters cycle through N unique states (e.g., MOD-8 counts 000 to 111, then resets).

Key Definitions

Why Counters Matter

Counters are ubiquitous in digital systems for:

• Timing applications: Generating clock pulses (e.g., NTC’s power grid monitoring).
• Memory addressing: Sequential access in RAM/ROM (e.g., Daraz’s order processing).
• Event counting: Packet routing in networks (e.g., Ncell’s call duration tracking).
• State machines: Finite state machines in CPUs (e.g., Google’s data center scheduling).

2. Asynchronous (Ripple) Counters

How It Works

• Each flip-flop’s output (Q) acts as the clock input for the next flip-flop.
• Propagation delay: The time taken for the last flip-flop to respond to a clock pulse accumulates, making ripple counters slower for large bit sizes.
• Design steps:
  1. Choose flip-flop type (JK/T/D).
  2. Connect Qₙ of flip-flop n to the clock input of flip-flop n+1.
  3. Reset the counter to 000...0 at power-up.

Example: 3-bit Asynchronous Up Counter (Using JK Flip-Flops)

Step 1: State Diagram

stateDiagram-v2
    [*] --> 000
    000 --> 001
    001 --> 002
    002 --> 003
    003 --> 004
    004 --> 005
    005 --> 006
    006 --> 007
    007 --> [*]

Step 2: Excitation Table

Step 3: Logic Diagram

Step 4: Timing Diagram

• Observation: The output Q2 lags behind Q0 and Q1 due to ripple delay.

Advantages/Disadvantages

3. Synchronous Counters

How It Works

• All flip-flops share the same clock input, eliminating ripple delay.
• Enable inputs: Used to control counting (e.g., LOAD or ENABLE signals).
• Design steps:
  1. Derive the excitation table from the state diagram.
  2. Simplify Boolean expressions for flip-flop inputs.
  3. Implement using gates or programmable logic.

Example: 3-bit Synchronous Up Counter (Using T Flip-Flops)

Step 1: State Diagram (Same as above) Step 2: Excitation Table (T flip-flop toggles when T=1)

Step 3: Boolean Expressions

• T₀ = 1 (always toggles).
• T₁ = Q₀ (toggles when Q₀=1).
• T₂ = Q₁ AND Q₀ (toggles when Q₁Q₀=11).

Step 4: Logic Diagram

Step 5: Timing Diagram

• Observation: No ripple delay; all flip-flops transition at the same time.

Advantages/Disadvantages

4. MOD-N Counters

A MOD-N counter cycles through N unique states before resetting. Design involves:

1. State diagram: Draw transitions for N states.
2. Excitation table: Map present/next states to flip-flop inputs.
3. Reset logic: Force counter to 000...0 after the N-th state.

Example: MOD-7 Counter (Asynchronous)

Step 1: State Diagram

stateDiagram-v2
    [*] --> 000
    000 --> 001
    001 --> 010
    010 --> 011
    011 --> 100
    100 --> 101
    101 --> 110
    110 --> [*]

Step 2: Excitation Table (JK Flip-Flops)

Step 3: Logic Diagram

Step 4: Timing Diagram

5. Registers: Types and Applications

A register is a group of flip-flops that stores binary data. Registers are classified by:

• Data transfer: Serial-in/serial-out (SISO), serial-in/parallel-out (SIPO), parallel-in/serial-out (PISO), parallel-in/parallel-out (PIPO).
• Shift direction: Left/right or bidirectional.

Types of Registers

Example: 4-bit SIPO Register (Storing "2001" in Binary)

Binary of 2001: 11111011001 (11 bits → use 4-bit for simplicity: 1111). Step 1: Block Diagram

flowchart LR
    subgraph Clock["Clock"]
    end
    subgraph DFF0["D FF (Q0)"]
        direction TB
        D0["D0=Serial In"] --> DFF0
        DFF0 --> Q0["Q0"]
    end
    subgraph DFF1["D FF (Q1)"]
        direction TB
        D1["D1=Q0"] --> DFF1
        DFF1 --> Q1["Q1"]
    end
    subgraph DFF2["D FF (Q2)"]
        direction TB
        D2["D2=Q1"] --> DFF2
        DFF2 --> Q2["Q2"]
    end
    subgraph DFF3["D FF (Q3)"]
        direction TB
        D3["D3=Q2"] --> DFF3
        DFF3 --> Q3["Q3"]
    end
    Clock --> DFF0
    Q0 --> DFF1
    Q1 --> DFF2
    Q2 --> DFF3

Step 2: Truth Table (Loading "1111")

Step 3: Timing Diagram

Bidirectional Shift Register

Example: 4-bit Bidirectional Register

flowchart LR
    subgraph Clock["Clock"]
    end
    subgraph DFF0["D FF (Q0)"]
        direction TB
        D0["D0=Serial In or Q1 (right shift)"] --> DFF0
        DFF0 --> Q0["Q0"]
    end
    subgraph DFF1["D FF (Q1)"]
        direction TB
        D1["D1=Q0 or Q2 (left/right shift)"] --> DFF1
        DFF1 --> Q1["Q1"]
    end
    subgraph DFF2["D FF (Q2)"]
        direction TB
        D2["D2=Q1 or Q3"] --> DFF2
        DFF2 --> Q2["Q2"]
    end
    subgraph DFF3["D FF (Q3)"]
        direction TB
        D3["D3=Q2 or Serial In (left shift)"] --> DFF3
        DFF3 --> Q3["Q3"]
    end
    Clock --> DFF0
    Clock --> DFF1
    Clock --> DFF2
    Clock --> DFF3
    subgraph Control["Control"]
        direction TB
        Mode["Mode=0 (Right)\nMode=1 (Left)"] --> D0
        Mode --> D1
        Mode --> D2
        Mode --> D3
    end

6. Ring Counter

A ring counter is a shift register where the output of the last flip-flop feeds back to the input, creating a circular shift. Example: 3-bit Ring Counter

flowchart LR
    subgraph Clock["Clock"]
    end
    subgraph FF0["JK FF (Q0)"]
        direction TB
        J0["J0=1"] --> FF0
        K0["K0=Q2"] --> FF0
        FF0 --> Q0["Q0"]
    end
    subgraph FF1["JK FF (Q1)"]
        direction TB
        J1["J1=Q0"] --> FF1
        K1["K1=Q0"] --> FF1
        FF1 --> Q1["Q1"]
    end
    subgraph FF2["JK FF (Q2)"]
        direction TB
        J2["J2=Q1"] --> FF2
        K2["K2=Q1"] --> FF2
        FF2 --> Q2["Q2"]
    end
    Clock --> FF0
    Clock --> FF1
    Clock --> FF2
    Q2 --> FF0

State Sequence: 100 → 010 → 001 → 100 ...

Applications:

• Traffic light controllers: Cyclic sequencing.
• Round-robin scheduling: CPU task switching.
• Serial data transmission: Simple bit circulation.

In the Real World

1. eSewa’s Transaction Counter

   • Idea Used: MOD-N counters track transaction IDs (e.g., MOD-10000 for unique IDs).
   • How: A synchronous counter increments with each transaction, resetting after 10000 to avoid ID collisions.

2. Pathao’s Order Queue

   • Idea Used: Priority encoders + counters manage rider assignments.
   • How: A counter assigns order IDs, while a priority encoder selects the next available rider (like a round-robin scheduler using a ring counter).

3. NTC’s Power Grid Monitoring

   • Idea Used: Asynchronous counters measure voltage cycles.
   • How: A ripple counter counts AC cycles (50Hz → 20ms per cycle), triggering alerts if cycles exceed thresholds.

4. Khalti’s Payment Timeout

   • Idea Used: Synchronous counters enforce timeouts.
   • How: A 16-bit counter with a 1Hz clock times out after 65536 seconds (~18 hours), aborting pending transactions.

5. NEPSE Stock Ticker

   • Idea Used: Shift registers display stock prices.
   • How: A SIPO register shifts price data serially from the server to a parallel display (e.g., LED matrix).

6. WhatsApp’s Message Encryption

   • Idea Used: Bidirectional shift registers in AES encryption.
   • How: Data is shifted left/right during key expansion, mixing bits for security.

Exam Tip

1. Design Questions:

   • Always show state diagrams, excitation tables, and logic diagrams for full marks.
   • For MOD-N counters, highlight the reset condition (e.g., "110 → 000" in MOD-7).
   • Use K-maps to simplify flip-flop input equations if asked.

2. Differentiation:

   • Asynchronous vs. Synchronous:
     • Asynchronous: "Clock derived from previous flip-flop’s output."
     • Synchronous: "All flip-flops share the same clock input."
   • Register Types:
     • SIPO: "Serial in, parallel out (e.g., memory buffer)."
     • PISO: "Parallel in, serial out (e.g., printer data)."

3. Timing Diagrams:

   • Label clock edges, propagation delays (for ripple counters), and state transitions.
   • For synchronous counters, show simultaneous changes at the clock edge.

4. Common Pitfalls:

   • Forgetting to reset the counter in MOD-N designs.
   • Misaligning flip-flop inputs (e.g., using J=K=1 for toggling but not accounting for reset).
   • Ignoring load/enable signals in practical designs.

5. Real-World Tie-Ins:

   • Relate counters to timing (e.g., "NTC’s AC cycle counter").
   • Link registers to data storage (e.g., "eSewa’s transaction ID register").
   • Use bidirectional shift registers for encryption examples (e.g., "WhatsApp’s AES").

Practice Problems

1. Design a 4-bit synchronous down counter using D flip-flops. Show the state diagram, excitation table, and logic diagram.
2. Modify the MOD-7 counter to count up and down (bidirectional) using a control input.
3. Explain how a ring counter can be used to implement a traffic light controller with 4 states (red → green → yellow → repeat).
4. Draw the timing diagram for a 3-bit asynchronous counter with inputs A=1 (load) and B=1 (enable counting). Show the behavior when A goes high during counting.