8085 Microprocessor: Architecture, Blocks & Bus Organization

TAKEAWAYS:

• The 8085 microprocessor is an 8-bit CPU with 40-pin DIP packaging, featuring an ALU, registers (A, B, C, D, E, H, L, SP, PC, PSW), and control unit interconnected via three buses (address, data, control).
• Functional blocks include the ALU (arithmetic/logic operations), register array (temporary storage), control unit (instruction decoding/execution), and timing & control circuits (clock generation).
• Bus organization uses multiplexed address/data bus (16-bit address, 8-bit data) and three control signals (RD, WR, INTR) for memory/I/O communication.
• Signal types are classified as input (RESET, INTR, CLK), output (HLDA, INTA), and bidirectional (AD7-AD0, SID/SOD).
• Real-world use: The 8085 powers legacy calculators, industrial controllers (e.g., NTC’s old billing systems), and embedded systems like traffic light controllers.
• Exam focus: Expect block diagrams, signal explanations, and comparisons with modern CPUs (e.g., 8086).

1. Introduction to the 8085 Microprocessor

The 8085 is an 8-bit microprocessor introduced by Intel in 1976, widely used in early computers, embedded systems, and educational labs. It operates at clock speeds of 3 MHz and supports 256 KB of memory (16-bit address bus). Unlike modern CPUs, it lacks a separate memory management unit (MMU) and relies on hardwired control logic.

Key Features

• 8-bit data bus (8-bit ALU, 8-bit registers).
• 16-bit address bus (64 KB addressable memory).
• 5 internal registers (A, B, C, D, E) and 3 special-purpose registers (H, L, SP, PC, PSW).
• 74 LS series TTL-compatible I/O.
• Interrupt-driven architecture (5 interrupt sources: TRAP, RST 7.5, RST 6.5, RST 5.5, INTR).

2. Functional Blocks of the 8085

The 8085’s architecture is divided into five major functional blocks:

A. Arithmetic Logic Unit (ALU)

Performs arithmetic (ADD, SUB, INC, DEC) and logic operations (AND, OR, XOR, COMP). Results are stored in the Accumulator (A) and affect flags in the PSW (Program Status Word).

stateDiagram-v2
    [*] --> ALU: Input (A, B, Immediate Data)
    ALU --> Result: Output (A, Flags)
    ALU --> PSW: Sets Flags (Z, S, P, CY, AC)

B. Register Array

Holds temporary data and addresses. Key registers:

C. Control Unit

Decodes instructions and generates control signals for ALU, registers, and buses. It uses a hardwired control unit (no microprogramming in 8085).

D. Timing and Control Circuits

Generates clock signals (CLK) and synchronizes operations via machine cycles (M1, M2, etc.) and T-states (clock pulses).

E. Interrupt Logic

Handles 5 interrupt sources (TRAP, RST 7.5, etc.) via the Interrupt Flip-Flop (IFF) and Interrupt Enable (EI/DI) instructions.

3. Bus Organization of the 8085

The 8085 uses three buses for communication:

Multiplexing: The lower 8 bits of the address bus (A7-A0) are multiplexed with the data bus (AD7-AD0) to reduce pin count.

       +---------------------+
       |      8085 CPU       |
       | +---------------+   |
       | |   ALU/Regs    |   |
       | +------+--------+   |
       |         |           |
       |         v           |
       | +-----------+       |
       | | Control  |       |
       | |  Unit    |       |
       | +-----------+       |
       |         |           |
       |         v           |
       +---------+-----------+
              / | \
             /  |  \
            /   |   \
           /    |    \
+-----------+    |    +-----------+
| Address  |<---+--->| Memory/I/O |
| Bus (A15- |       |           |
| A0/AD7-  |       |           |
| AD0)     |       |           |
+-----------+       +-----------+
       |           |
       v           v
+-----------+ +-----------+
| Data Bus  | | Control  |
| (AD7-AD0) | | Signals  |
+-----------+ +-----------+

4. Signal Types in 8085

Signals are classified into three categories:

Key Signals:

• RESET: Initializes CPU (PC = 0000H).
• INTR: Maskable interrupt request.
• HLDA: Hold Acknowledge (CPU releases buses for DMA).
• RDY: Ready signal (slows CPU for slow memory/I/O).

5. Real-World Applications of 8085

A. Legacy Systems in Nepal

1. NTC’s Old Billing Systems

   • Use: The 8085 was used in telephone billing machines in the 1990s–2000s to calculate call durations and charges.
   • How: Custom firmware ran on an 8085-based microcontroller to read pulse dialing inputs, compute tariffs, and print receipts.

2. Industrial Controllers (e.g., Water Pump Systems)

   • Use: Small-scale water level controllers in rural areas used 8085-based systems to monitor sensors and activate pumps.
   • How: Analog inputs (from float switches) were digitized via ADC, and the 8085 executed logic to turn relays on/off.

3. Educational Kits (e.g., 8085 Trainer Kits)

   • Use: Universities and polytechnics in Nepal (e.g., IOE, TU’s CACS labs) still use 8085 trainer boards to teach assembly programming and digital logic.
   • How: Students write programs (e.g., MVI A, 05H; OUT 01H) to control LEDs, 7-segment displays, and keypads.

B. Worked Example: Traffic Light Controller

Scenario: A simple traffic light system uses an 8085 to cycle through red, yellow, green for two roads. Program Snippet:

        MVI A, 01H       ; Load red light (01H = binary 00000001)
        OUT 02H          ; Send to port 02H (connected to relay)
        CALL DELAY       ; Delay for 30 seconds
        MVI A, 02H       ; Load green light (02H = 00000010)
        OUT 02H
        CALL DELAY
        JMP LOOP         ; Repeat
DELAY:  MOV C, 30       ; 30-second delay loop
        ... (assembly code for delay)
        RET

How It Works:

1. The 8085 reads a predefined pattern (e.g., 01H for red) from memory.
2. The OUT instruction sends the signal to a parallel port (8255 PPI), which controls relays.
3. The DELAY subroutine uses a software loop (or hardware timer) to pause execution.

6. Comparison: 8085 vs. Modern CPUs

7. Exam Tip: How to Score Full Marks

1. Draw the Block Diagram

   • Always sketch the 8085’s internal architecture (ALU, registers, control unit, buses) with labels. 5 marks are often allocated for this.

2. Explain Signal Flow

   • For questions like "Explain the bus organization," describe:
     • How A15-A8 are latched separately.
     • How AD7-AD0 are multiplexed.
     • The role of control signals (RD, WR).

3. Trace an Instruction Execution

   • For MVI A, 32H:
     • Fetch Cycle: PC → MAR → Memory → MDR → IR.
     • Execute Cycle: Immediate data (32H) loaded into A.
     • Mention T-states (e.g., 3 T-states for MVI).

4. Compare with 8086

   • Highlight differences in address/data bus separation, 16-bit registers, and segmented memory.

5. Real-World Link

   • If asked about applications, mention legacy systems (NTC billing), educational kits, or embedded controllers.

8. Practice Questions (Exam-Style)

1. Short Answer:

   • "What is the role of the Stack Pointer (SP) in 8085?" Answer: SP holds the 16-bit address of the top of the stack in RAM. Used for PUSH/POP operations (e.g., PUSH B stores BC on stack and decrements SP by 2).

2. Diagram-Based:

   • "Draw the internal architecture of 8085 and label the data path from the Accumulator to the ALU." Key Points:
     • Show A → ALU → Result → A.
     • Include PSW flags updated by ALU.

3. Programming:

   • "Write an 8085 assembly program to add two 8-bit numbers stored at memory locations 2100H and 2101H, and store the result at 2102H."

     MVI H, 21H       ; Load high byte of address
     MVI L, 00H       ; Load low byte (2100H)
     MOV A, M         ; Load data from 2100H into A
     INX H            ; Increment L to point to 2101H
     ADD M            ; Add data from 2101H to A
     INX H            ; Increment to 2102H
     MOV M, A         ; Store result at 2102H
     HLT
     

4. Explain:

   • "Why is the 8085’s address/data bus multiplexed?" Answer: To reduce pin count (40-pin DIP package). The lower 8 address bits (A7-A0) share pins with the data bus (AD7-AD0) via a multiplexer, saving 8 pins.

9. Common Mistakes to Avoid

• Forgetting Multiplexing: Many students draw separate address and data buses. Always show AD7-AD0 as multiplexed.
• Incorrect Flag Updates: After SUB B, the Zero (Z), Sign (S), Carry (CY), and Auxiliary Carry (AC) flags change. List all affected flags.
• Ignoring T-States: Questions on instruction execution (e.g., MVI A, 32H) require mentioning T-states (e.g., 3 T-states for MVI).
• Mixing 8085 and 8086: The 8086 has a 16-bit data bus and separate address/data buses. Never confuse them.

10. Summary Table: Key Components

11. Final Visual: 8085 Instruction Cycle

sequenceDiagram
    participant PC as Program Counter
    participant MAR as Memory Address Register
    participant MDR as Memory Data Register
    participant IR as Instruction Register
    participant CU as Control Unit
    participant ALU as Arithmetic Logic Unit

    Note over PC,CU: Fetch Cycle
    PC->>MAR: Send address (A15-A0)
    MAR->>Memory: Fetch instruction
    Memory->>MDR: Return instruction bytes
    MDR->>IR: Load into IR
    IR->>CU: Decode instruction
    CU->>PC: Increment PC

    Note over CU,ALU: Execute Cycle
    CU->>ALU: Perform operation (e.g., ADD)
    ALU->>A: Store result in Accumulator
    CU->>Flags: Update PSW