CACS155 Microprocessor and Computer Architecture

Microprocessor and Computer ArchitectureUnit 513 min read

Control Unit: Hardwired vs. Microprogrammed Design

Unit 5 of Microprocessor and Computer Architecture explores the control unit—the brain of the CPU—comparing hardwired (direct logic gates) and microprogrammed (sequenced control words) designs, their trade-offs, and real-world applications in modern processors like those in eSewa payment systems or Ncell’s billing serv

TAKEAWAYS

  • The control unit (CU) decodes instructions and generates timing/control signals for CPU operations using either hardwired logic (fast, rigid) or microprogrammed logic (flexible, slower).
  • Hardwired CU uses combinational logic gates for each instruction, offering high speed but low flexibility (changes require hardware redesign).
  • Microprogrammed CU stores control sequences in control memory (microprogram ROM), enabling easy modifications (e.g., adding new instructions) but adding overhead (extra fetch/decode cycles).
  • Control words are bit-patterns that activate signals (e.g., "load ALU input from register A")—each instruction maps to a sequence of these words.
  • Microprogram sequencers (sequential or parallel) determine the next microinstruction address via next-address field or sequencer logic.
  • Real-world tie: Ncell’s billing servers use microprogrammed CUs for dynamic tariff updates, while eSewa’s payment processors rely on hardwired CUs for ultra-low-latency transactions.

1. The Role of the Control Unit (CU)

The control unit is the decision-making and timing coordinator of the CPU. Its primary functions are:

  1. Fetch: Retrieve instructions from memory via the program counter (PC).
  2. Decode: Interpret the instruction’s opcode to determine the operation (e.g., ADD, JMP).
  3. Execute: Generate control signals (e.g., "load data bus," "clock ALU") to coordinate CPU components (ALU, registers, memory).
  4. Synchronize: Manage timing via clock cycles and machine cycles (e.g., M1: fetch, M2: execute).

A labelled diagram showing the CU’s connection to the ALU, registers, memory, and buses.


2. Hardwired Control Unit: Direct Logic Gates

opcodecontrol signalscontrol signalscontrol signalsIRALURegistersMemoryControl Logic
Hardwired CU block diagram (8085-style)

How It Works

  • Uses combinational logic circuits (AND/OR/NOT gates) hardcoded for each instruction.
  • For example, the ADD instruction might trigger:
    • Load A → ALU input 1
    • Load B → ALU input 2
    • Set ALU op-code to ADD
    • Write result to ACC
  • No memory lookup: Control signals are generated directly from the instruction bits.

Worked Example: Hardwired MOV A,B in 8085

Assume the 8085’s CU has logic for MOV A,B (move data from register B to accumulator A):

  1. Instruction: 10000010 (binary opcode for MOV A,B).
  2. CU logic:
    • Decodes 10000010 → activates signals:
      • REG_SEL = 11 (select register B)
      • MEM_READ = 0 (data from register, not memory)
      • ALU_SRC = REG_OUT (source is register output)
      • ACC_WRITE = 1 (write to accumulator)
  3. Result: Data from B is copied to A in 1 machine cycle.

Advantages

Pros Explanation
Speed No extra memory access; signals generated instantly.
Simplicity Fewer components (no control memory).
Power Efficiency Less overhead than microprogrammed CUs.

Disadvantages

Cons Explanation
Rigidity Adding a new instruction requires redesigning hardware.
Complexity Logic grows exponentially with more instructions.
Error-Prone Hard to debug; changes need physical rewiring.

A diagram showing how the 8085’s ADD instruction might be implemented with gates for ALU control signals.


3. Microprogrammed Control Unit: Control Memory

How It Works

  • Instead of hardwired logic, the CU uses a microprogram—a sequence of microinstructions stored in control memory (ROM).
  • Each microinstruction is a control word that specifies:
    • Control signals (e.g., "load ALU input from register X").
    • Next microinstruction address (sequential or conditional).
  • Example: The ADD instruction might require 5 microinstructions:
    1. Load operand 1 to ALU.
    2. Load operand 2 to ALU.
    3. Set ALU to ADD mode.
    4. Write result to accumulator.
    5. Increment PC.

Key Components

Instruction Register (IR)Microaddress Register (μAR)Control Memory (ROM)Control WordControl SignalsNext μARALU/Registers/Memorydata flow
Microprogrammed Control Unit data flow (feedback loop shown with dashed arrow)

Control Word Structure

A typical control word has:

Field Bits Purpose
Next μAR 8–16 Address of the next microinstruction.
Control Signals 16–64 Activates ALU, registers, buses (e.g., MEM_RD, ACC_WR).
Conditional Flags 4–8 For branching (e.g., ZF=1 for zero flag).
0481215Opcode Field4 bitsRegisterSelect3 bitsALU Control4 bitsMemory Control3 bitsTimingSignals2 bits
Typical 16-bit microinstruction control word format (8085 example)

A labelled diagram of a 16-bit control word for the 8085, showing fields for next address and control signals.


4. Microprogram Sequencing

The microprogram sequencer determines the next microinstruction address. Two types:

A. Sequential (Straightforward) Sequencing

  • Next address = current address + 1 (like a program counter).
  • Pros: Simple, fast for linear sequences.
  • Cons: Cannot handle branches or loops easily.

B. Conditional Sequencing

  • Uses flags (e.g., zero flag ZF, carry flag CF) to decide the next address.
  • Example: After an ADD, check CF to branch to overflow handling.
  • Implemented via:
    • Next-address field: Hardcoded in the control word.
    • Sequencer logic: Uses flags to compute the next address.

A diagram showing how the 8085’s sequencer uses the ZF flag to branch to a microinstruction for JZ (jump if zero).


5. Hardwired vs. Microprogrammed: Comparison

Feature Hardwired Control Unit Microprogrammed Control Unit
Implementation Combinational logic gates. Control memory (ROM) + sequencer.
Speed Faster (no memory access). Slower (extra fetch/decode cycle).
Flexibility Rigid (hardware changes needed). Flexible (software changes via microcode).
Complexity High for complex instructions. Moderate (sequencer logic).
Cost Lower (no control memory). Higher (ROM/sequencer adds cost).
Modification Difficult (requires redesign). Easy (update microprogram).
Power Consumption Lower (no extra memory access). Higher (sequencer overhead).
Example Use Case eSewa payment processors (low latency). Ncell billing servers (dynamic tariffs).

6. Real-World Applications

A. eSewa: Hardwired CU for Low-Latency Transactions

  • Why? eSewa’s servers process thousands of transactions/sec (e.g., mobile top-ups, bill payments).
  • How? Uses hardwired CUs in custom ASICs (Application-Specific Integrated Circuits) for:
    • Instant validation of payment requests.
    • Direct routing of funds without microprogram overhead.
  • Result: Transactions complete in <50ms, critical for user experience.

B. Ncell: Microprogrammed CU for Dynamic Tariff Updates

  • Why? Ncell’s billing system must handle changing tariffs (e.g., night-time discounts, bundle offers).
  • How? Uses microprogrammed CUs to:
    • Reconfigure pricing logic via software updates (no hardware changes).
    • Add new tariff rules without halting services.
  • Example: When a new "Happy Hours" tariff is launched, the microprogram is updated to apply discounts during 2–5 AM.

C. Google’s TPUs: Hybrid Approach

  • Tensor Processing Units (TPUs) used in Google’s data centers combine:
    • Hardwired logic for matrix operations (fast matrix multiplication).
    • Microprogrammed control for dynamic workload scheduling.
  • Result: 90% faster than CPUs for AI training while allowing flexibility.

7. Worked Example: Microprogram for 8085 FETCH Cycle

Instruction: LDA 2100H (Load A from memory address 2100H). Microprogram Steps (simplified):

Step Microinstruction Control Signals Next μAR
1 Load PC → MAR (Memory Address Register) PC→MAR=1, MAR_LD=1 2
2 Read memory → MB (Memory Buffer) MEM_RD=1, MB_LD=1 3
3 Load MB → IR (Instruction Register) MB→IR=1, IR_LD=1 4
4 Decode IR → set next μAR for LDA IR_DECODE=1 (branches to LDA microprogram) LDA_start

Mermaid Diagram:

CU fetches μARfrom PCMemory read(MB_RD=1, MB_LD=1)MB → IR (MB→IR=1,IR_LD=1)Branch to LDAmicroprogram (IR_DECOD
8085 FETCH cycle microprogram sequencing (4-step breakdown)

8. Designing a Microprogrammed CU: Step-by-Step

  1. List all instructions (e.g., ADD, SUB, JMP).
  2. Break each into microoperations (e.g., ADD → load A, load B, ALU ADD, write result).
  3. Assign control signals to each microoperation (e.g., REG_A→ALU=1).
  4. Design the control word format (e.g., 16 bits: 8 for next address, 8 for signals).
  5. Write the microprogram (sequence of control words).
  6. Implement the sequencer (sequential or conditional).
  7. Test with sample instructions (e.g., trace MOV A,B).

A diagram of a 256-word × 16-bit control memory storing microinstructions for the 8085.


Exam Tip

  1. Compare hardwired vs. microprogrammed:

    • Exam loves this table—memorize pros/cons for speed, flexibility, and cost.
    • Example answer: "Hardwired CUs are used in high-speed applications like eSewa’s payment gateways due to their low latency, while microprogrammed CUs in Ncell’s billing systems allow dynamic tariff updates without hardware changes."
  2. Control word structure:

    • Draw it in exams. Label fields like next μAR and control signals.
    • Example: For a 16-bit control word, show 8 bits for address and 8 for signals.
  3. Microprogram sequencing:

    • Explain both types (sequential vs. conditional) with a small example (e.g., branching on ZF=1).
    • Diagram tip: Use a state diagram to show how the sequencer moves between microinstructions.
  4. Real-world tie-ins:

    • Always link to Nepalese examples (e.g., "Like how Ncell updates tariffs via microprograms, TU’s student database might use hardwired CUs for fast grade processing").
    • Avoid vague answers: Specify which part of the system uses which CU (e.g., "The payment validation ASIC in eSewa uses hardwired control").
  5. Common pitfalls:

    • Don’t confuse microinstructions with machine instructions.
      • ❌ "The 8085’s ADD instruction is a microinstruction." (Wrong!)
      • ✅ "The 8085’s ADD instruction is implemented via 5 microinstructions in its microprogrammed CU."
    • Don’t forget the sequencer: Exams often ask how the next microinstruction is selected—always mention the sequencer logic.

Practice Questions (Exam-Style)

  1. Short Answer:

    • "Why would a microprogrammed CU be preferred over a hardwired one for a system that frequently updates its instruction set?"
    • Answer: "Microprogrammed CUs allow software-based modifications to the instruction set (via microcode updates), while hardwired CUs require expensive hardware redesigns. This makes them ideal for dynamic systems like Ncell’s billing servers where tariff rules change often."
  2. Diagram-Based:

    • "Draw the control word format for a microprogrammed CU that supports 256 microinstructions and 32 control signals. Label all fields."
    • Answer:
      +---------------------+
      | Next μAR (8 bits)    |  (256 possible addresses)
      +---------------------+
      | Control Signals (8)  |  (e.g., MEM_RD, ACC_WR)
      |     ...             |
      | Control Signals (8)  |
      +---------------------+
      
  3. Comparison:

    • "Compare the speed and flexibility of hardwired and microprogrammed CUs. Provide one Nepalese and one global example for each."
    • Answer:
      Aspect Hardwired CU Microprogrammed CU
      Speed Faster (eSewa’s ASICs) Slower (Ncell’s billing servers)
      Flexibility Rigid (Google TPUs) Flexible (Intel’s x86 microcode)

Based on the TU BCA syllabus for Microprocessor and Computer Architecture (CACS155), unit 5.

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