Instruction Execution: Cycles, T-States & 8085 Timing

TAKEAWAYS:

• An instruction cycle is the complete process of fetching, decoding, and executing an instruction, consisting of one or more machine cycles.
• Each machine cycle (e.g., fetch, memory read/write, I/O) is divided into T-states (clock pulses), with the 8085 using a 3 MHz clock (each T-state = 1/3 μs).
• The opcode fetch cycle is mandatory for every instruction and always takes 4 T-states (1 machine cycle).
• Memory read/write cycles take 3 T-states (1 machine cycle) for 8085, while I/O cycles take 4 T-states.
• Timing diagrams show signal transitions (e.g., ALE, RD, WR, SYNC) during each T-state to visualize execution.
• Real-world applications use these principles in embedded systems (e.g., traffic light controllers, ATM machines) where precise timing is critical.

1. Instruction Cycle: The Full Execution Journey

The instruction cycle is the complete sequence a microprocessor follows to execute a single instruction. It consists of four stages:

1. Fetch: Retrieve the opcode from memory.
2. Decode: Interpret the opcode to determine the operation.
3. Execute: Perform the operation (e.g., data transfer, arithmetic, I/O).
4. Store (if needed): Write results back to memory/registers.

sequenceDiagram
    participant CPU as 8085 CPU
    participant Memory as RAM
    participant Registers as Internal Registers

    CPU->>Memory: Fetch Opcode (4 T-states)
    Memory-->>CPU: Returns 06H (MVI)
    CPU->>Registers: Decode (Internal)
    CPU->>Memory: Fetch Operand (3 T-states)
    Memory-->>CPU: Returns 32H
    CPU->>Registers: Write to A (Internal)
    Note over CPU: Total: 7 T-states (external) + 3 (internal)

Instruction Cycle for MVI A, 32H (Opcode + Operand Fetch)

For most 8085 instructions, this cycle requires multiple machine cycles (e.g., MVI A, 32H needs 3 machine cycles: opcode fetch, memory read for operand, and write-back).

Why it matters:

• The 8085 cannot execute an instruction without completing the fetch cycle first.
• Some instructions (e.g., NOP) take only 1 machine cycle, while others (e.g., DAD B) take 3.

2. Machine Cycle: The Building Blocks

A machine cycle is a group of T-states that accomplish a specific task, such as:

• Opcode fetch (always required).
• Memory read/write (for operands or results).
• I/O read/write (for peripheral communication).

Each machine cycle has a fixed number of T-states (clock pulses) for the 8085:

Key signals during a machine cycle:

• ALE (Address Latch Enable): Latches the low byte of the address.
• RD (Read): Pulled low to read from memory/I/O.
• WR (Write): Pulled low to write to memory/I/O.
• SYNC: Indicates the start of a machine cycle.

3. T-States: The Clock’s Pulse

A T-state is the smallest unit of time in the 8085, defined by its 3 MHz clock (each T-state = 1/3 μs or ~333 ns).

Each machine cycle consists of 3 to 4 T-states, divided into:

1. T1: Address and control signals are set.
2. T2: Data transfer occurs (if applicable).
3. T3: Next operation begins (e.g., next memory access).
4. T4 (optional): Used in I/O cycles or some instructions.

Example: MVI A, 32H Execution Let’s trace the execution of MVI A, 32H (Move immediate value 32H to accumulator A):

Total time: 10 T-states (4 + 3 + 3, but the last write is internal).

4. Real-World Applications: Where Timing Matters

📱 eSewa Payment Processing

• When you pay a bill via eSewa, the 8085-like microcontroller in the payment terminal must:
  1. Fetch the payment instruction from memory.
  2. Read the card data (memory read cycle).
  3. Send the transaction to the bank (I/O write cycle).
• If the T-state timing is miscalculated, the transaction may fail or corrupt data.

🚗 Traffic Light Controller (Using 8085)

• A traffic light system uses an 8085-based microcontroller to cycle through red/green lights.
• The instruction cycle must complete in fixed intervals (e.g., 30 seconds for green).
• If a JMP instruction takes 12 T-states, the controller must account for this delay to avoid timing errors.

💳 ATM Machine (Embedded Systems)

• ATMs use microprocessors to:
  1. Fetch the "dispense cash" instruction.
  2. Read the account balance from memory.
  3. Write the new balance back to memory.
• A single T-state delay can cause a ₹1000 discrepancy in transactions!

5. Worked Example: Timing Analysis for DAD B (Add HL to DE)

The DAD B instruction adds the contents of register B (extended to 16 bits) to the HL register pair. Execution steps:

1. Opcode fetch (DAD B = 09H) → 4 T-states.
2. Memory read (not needed, as operand is in B) → 0 T-states (internal).
3. Execute addition → 3 T-states (internal).
4. Write result to HL → 3 T-states (internal).

Total: 10 T-states (but only 4 T-states are externally visible due to opcode fetch).

Timing diagram:

6. Comparison: Instruction Cycle vs. Machine Cycle vs. T-State

7. Exam Tip: How to Score Full Marks

✅ Define clearly:

• Instruction cycle = Fetch → Decode → Execute → Store.
• Machine cycle = Group of T-states for a task (fetch, read, write).
• T-state = Single clock pulse (1/3 μs).

✅ Draw timing diagrams:

• Always show T1-T4 for opcode fetch.
• Label signals (ALE, RD, WR) correctly.
• Use real examples (e.g., MVI A, 32H trace).

✅ Calculate total T-states:

• For LDA 2000H:
  • Opcode fetch: 4 T-states.
  • Memory read: 3 T-states.
  • Total = 7 T-states.

✅ Avoid common mistakes:

• ❌ Saying "T-state = machine cycle" (they are different!).
• ❌ Forgetting that opcode fetch is always 4 T-states.
• ❌ Not showing signal transitions in timing diagrams.

Final Note: The 8085’s instruction execution is all about timing precision. Mastering machine cycles and T-states will help you ace questions on instruction timing, embedded systems, and real-world microcontroller applications in exams! 🚀