Digital Logic Applications & Problem-Solving

Key Concepts & Problem-Solving Frameworks

1. Design Methodology for Digital Systems

Digital systems are built using a structured approach:

1. Problem Analysis: Define inputs, outputs, and constraints (e.g., cost, speed, power).
2. Logic Design: Choose between combinational or sequential circuits based on requirements.
3. Simulation & Verification: Use tools like Logisim or Vivado to test designs before hardware implementation.
4. Optimization: Simplify using K-maps, Boolean algebra, or PLDs (covered in Unit 6).
5. Implementation: Map the design to real components (ICs, FPGAs, or microcontrollers).

2. Combinational vs. Sequential Circuit Applications

Why it matters:

• Combinational circuits are instantaneous (output depends only on current inputs).
• Sequential circuits remember state (output depends on past inputs), making them ideal for timing-sensitive tasks like traffic control.

In the Real World

1. eSewa’s Transaction Validation (Combinational Logic)

When you pay a bill via eSewa, the system uses AND/OR gates to validate:

• Input: User ID, PIN, amount, and bank approval.
• Output: "Transaction Approved" or "Rejected." How it works:
• A priority encoder checks if the user’s PIN matches the database (sequential check).
• A multiplexer selects the correct bank’s validation logic (combinational).
• Final AND gate: Only outputs "Approved" if all conditions (PIN, balance, bank approval) are met.

flowchart LR
    A["User Inputs\n(User ID, PIN, Amount)"] --> B["PIN Validator\n(Sequential Check)"]
    B --> C["Bank Approval\n(Combinational Logic)"]
    C --> D["Multiplexer\n(Selects Bank Logic)"]
    D --> E["AND Gate\n(Final Approval)"]
    E --> F["Output:\nApproved/Rejected"]

2. Pathao’s Route Optimization (Sequential Logic & State Machines)

Pathao’s app uses a finite state machine (FSM) to handle rider requests:

• States: "Idle," "Rider Requested," "Driver Assigned," "Trip Ongoing," "Trip Completed."
• Transitions: Triggered by inputs like GPS location, rider cancellation, or destination reached. Why an FSM?
• Ensures no race conditions (e.g., driver assignment before rider request).
• Reduces errors in high-traffic scenarios (e.g., Kathmandu’s chaotic routes).

3. NTC’s Network Traffic Control (Priority Encoders & Decoders)

NTC’s fiber-optic network uses priority encoders to handle data packets:

• Problem: Multiple devices (e.g., schools, hospitals) send data simultaneously.
• Solution: A priority encoder assigns higher priority to critical traffic (e.g., hospitals over streaming).
• Output: A decoder routes the packet to the correct server.

Real-world impact:

• Prevents network congestion during peak hours (e.g., exam results day).
• Ensures low-latency for emergency services.

Worked Example: Traffic Light Controller (Sequential Circuit)

Problem: Design a traffic light system for a Kathmandu intersection with 3 states: Green (30s), Yellow (5s), Red (25s). Use a counter + decoder.

Step 1: Define States & Transitions

Step 2: Use a Mod-60 Counter (30+5+25=60s cycle)

• Counter: Counts from 0 to 59 using a 4-bit binary counter (since $2^6=64>60$).
• Decoder: Converts counter output to traffic light signals.

flowchart LR
    A["Clock\n(1Hz)"] --> B["4-bit Counter\n(0 to 59)"]
    B --> C["Decoder\n(Routes to Traffic Lights)"]
    C --> D["Green\n(0-29)"]
    C --> E["Yellow\n(30-34)"]
    C --> F["Red\n(35-59)"]
    F -->|"Overflow"| B

Step 3: Circuit Implementation

1. Counter: Use 4 T-flip-flops (connected as a ripple counter).
2. Decoder: Use a 3-to-8 decoder (74LS138) to activate the correct light.

Step 4: Timing Diagram

sequenceDiagram
    participant CLK as 1Hz Clock
    participant Counter as 6-bit Counter
    participant Decoder as 3-to-8 Decoder
    participant Lights as Traffic Lights

    loop Every 60s
        CLK->>Counter: Tick
        Counter->>Decoder: Q[5:0]
        Decoder->>Lights: Green (0-29)
        CLK->>Counter: Tick
        Counter->>Decoder: Q[5:0]
        Decoder->>Lights: Yellow (30-34)
        CLK->>Counter: Tick
        Counter->>Decoder: Q[5:0]
        Decoder->>Lights: Red (35-59)
    end

Common Problem-Solving Techniques

1. Troubleshooting Logic Circuits

Example: If eSewa’s transaction system fails to approve payments, check:

• AND gate inputs: Is the PIN validator outputting 1?
• Multiplexer selection: Is the correct bank’s logic being chosen?

2. Optimizing for Speed vs. Power

Example: NTC’s network uses low-power CMOS decoders to save energy, even if it means slightly slower routing.

Exam Tip

What Examiners Look For

1. Correct Circuit Design:

   • Always draw standard gate symbols (no ASCII art).
   • Label all inputs/outputs clearly.
   • Show state transitions for sequential circuits (use timing diagrams).

2. Real-World Mapping:

   • 20% of marks are for linking theory to applications (e.g., "How would you design a traffic light system for Pokhara?").
   • Avoid vague answers: Instead of "use a counter," say:

     "A 6-bit counter (0-63) with a decoder routes signals every 60s, using a 1Hz clock derived from a crystal oscillator for accuracy."

3. Troubleshooting Questions:

   • Expect scenario-based problems (e.g., "The output is always 0. Debug the circuit").
   • Step-by-step reasoning is key. Example:

     "1. Check power supply to the IC (should be 5V). 2. Verify all gate inputs are connected (use a multimeter). 3. Test individual gates in isolation."

4. K-Map Simplification:

   • Always show groups (even if obvious).
   • State the simplified Boolean expression and draw the minimized circuit.

Common Pitfalls

• Assuming all inputs are active high: Some gates (e.g., NAND) have inverted outputs.
• Ignoring propagation delay: In high-speed circuits, gate delays can cause errors.
• Overcomplicating designs: Use the simplest logic possible (e.g., a MUX instead of nested AND/OR gates).

Final Checklist Before Submitting

✅ Combinational circuits: Show truth table + simplified Boolean expression + gate diagram. ✅ Sequential circuits: Draw state diagram + excitation table + flip-flop connections. ✅ Real-world link: Relate to one Nepalese or global tech product (e.g., "This is how Pathao’s FSM avoids driver-rider mismatches"). ✅ Optimization: Mention speed vs. power trade-offs if applicable.

In the real world

• eSewa/Khalti: Uses priority encoders to validate transactions in milliseconds by checking user ID, PIN, and bank approval via combinational logic (AND/OR gates). If any input fails (e.g., wrong PIN), the final AND gate outputs 0 (reject).
• Pathao/Grab: Employs finite state machines (FSMs) to handle rider requests, driver assignments, and trip completion states. For example, the state Rider Requested transitions to Driver Assigned only after GPS confirms the driver’s location (sequential logic).
• NTC’s fiber-optic network: Deploys priority encoders to route emergency traffic (e.g., hospitals) ahead of non-critical data (e.g., streaming). A decoder then directs packets to the correct server, ensuring low latency for critical services.