Sequential Circuits & State Machines: Flip-Flops, Counters, FSMs, Timing

TAKEAWAYS:

• Sequential circuits remember past inputs via feedback, unlike combinational circuits that depend only on current inputs.
• Flip-flops (D, JK, T, SR) are the building blocks of memory and sequential logic, with master-slave configurations for edge-triggering.
• Counters (ripple, synchronous) and registers (shift, ring) are designed using flip-flops and are critical in clocked systems (e.g., CPU program counters).
• Finite State Machines (FSMs) model sequential behavior with states, transitions, and outputs, classified as Moore (outputs depend only on state) or Mealy (outputs depend on state + input).
• Timing diagrams are essential for analyzing race conditions, glitches, and setup/hold violations in sequential circuits.
• Design methods include state reduction, state assignment, and excitation tables to convert FSM specifications into hardware.

Sequential vs. Combinational Circuits

Sequential circuits store information (memory) and their outputs depend on current inputs + past states, unlike combinational circuits (AND, OR, XOR gates) that depend only on current inputs.

flowchart LR
    A["Combinational\nCircuits"] -->|"No Memory"| B["Output = f(Input)\n(AND, OR, XOR, MUX)"]
    C["Sequential\nCircuits"] -->|"Memory (Flip-Flops)"| D["Output = f(Input, State)\n(Counters, Registers, FSMs)"]
    B -->|"Example: ALU"| E["No clock needed"]
    D -->|"Example: CPU<br/>Registers"| F["Clock-driven\n(Edge-triggered)"]

Why does this matter?

• Combinational circuits are faster (no memory delay) but cannot remember.
• Sequential circuits are slower (due to clock) but enable memory, timing, and control (e.g., a bank ATM remembers your PIN across transactions).

Flip-Flops: The Memory Element

Flip-flops are clocked bistable multivibrators that store 1 bit and change state on a clock edge. They are the fundamental building blocks of sequential circuits.

Types of Flip-Flops

Type	Symbol (Standard)	Inputs	Key Feature	Applications
SR		S, R, Clock	Asynchronous reset/set (level-triggered)	Simple memory elements
D		D, Clock	Direct data transfer (D → Q)	Registers, data storage
JK		J, K, Clock	Universal flip-flop (can emulate SR, D, T)	Counters, sequential circuits
T		T, Clock	Toggle on T=1	Binary counters

Master-Slave Configuration

To avoid race conditions, flip-flops use a master-slave structure where:

1. Master flip-flop captures input on the first clock edge.
2. Slave flip-flop outputs the master’s state on the second edge. This ensures edge-triggered behavior (no glitches).

flowchart LR
    A["Clock"] -->|"Rising Edge"| B["Master Flip-Flop\n(Captures Input)"]
    B --> C["Slave Flip-Flop\n(Outputs on next edge)"]
    C -->|"Q"| D["Output"]
    A -->|"Falling Edge"| C

Worked Example: D Flip-Flop Operation Assume a D flip-flop with initial state $Q=0$. Draw the timing diagram for inputs $D=1$ and clock pulses.

Visual:

Counters: Sequential Circuit Applications

Counters are sequential circuits that increment/decrement on clock pulses. They use flip-flops and are classified as:

1. Asynchronous (Ripple) Counters: Flip-flops connected in cascade (each flip-flop’s output clocks the next).
2. Synchronous Counters: All flip-flops clocked simultaneously (faster, no propagation delay).

Ripple Counter (Asynchronous)

Design: Each flip-flop’s output is the clock input for the next flip-flop. Example: 3-bit binary counter using T flip-flops.

flowchart LR
    A["Clock"] --> B["T Flip-Flop 0\n(Q0)"]
    B --> C["T Flip-Flop 1\n(Q1)"]
    C --> D["T Flip-Flop 2\n(Q2)"]
    B -->|"Q0"| E["Output"]
    C -->|"Q1"| E
    D -->|"Q2"| E

Problem: Propagation delay increases with bits (slow for large counters). Solution: Use synchronous counters.

Synchronous Counter

Design: All flip-flops clocked simultaneously; use AND/OR gates for control signals. Example: 3-bit up-counter using JK flip-flops.

Advantages:

• Faster (no ripple delay).
• Used in CPU program counters, timers, and digital clocks.

Registers: Temporary Data Storage

Registers store multiple bits (e.g., 8-bit, 16-bit) and are built using flip-flops + control logic. Types:

1. Parallel Load Register: Loads data simultaneously on a load signal.
2. Shift Register: Shifts data left/right on clock pulses.
3. Ring Counter: Circular shift register (used in sequencers).

Example: 4-bit Parallel Load Register

Real-World Use:

• CPU registers (e.g., Accumulator, Program Counter).
• Memory buffers in Khalti transactions (storing temporary data during payment processing).

Finite State Machines (FSMs)

FSMs model sequential behavior with:

• States (e.g., "Idle", "Processing").
• Transitions (triggered by inputs).
• Outputs (Moore or Mealy).

Moore vs. Mealy Machines

Example: Traffic Light Controller (Moore Machine) States: Red, Green, Yellow. Transitions:

• Red → Green (after timer).
• Green → Yellow (after timer).
• Yellow → Red (immediately).

stateDiagram-v2
    [*] --> Red
    Red --> Green: Timer
    Green --> Yellow: Timer
    Yellow --> Red: Immediate

Worked Example: Vending Machine (Mealy Machine)

• States: Idle, Selecting, Dispensing.
• Outputs: Display message, release product.
• Transition: If coin inserted in "Selecting" → go to "Dispensing" and output "Product released".

Designing FSMs: Step-by-Step

1. State Diagram: Draw transitions and outputs.
2. State Reduction: Merge equivalent states.
3. State Assignment: Assign binary codes to states (e.g., Gray code to minimize glitches).
4. Excitation Tables: Determine flip-flop inputs (J, K, D, T) for each state transition.
5. Next-State and Output Equations: Use Boolean algebra to derive logic.
6. Implementation: Use flip-flops + combinational logic.

Example: Binary Sequence Detector (Detects "101")

Excitation Table for D Flip-Flops:

Timing Diagrams and Hazards

Timing diagrams show signal transitions over time and are critical for debugging sequential circuits.

Common Issues:

1. Race Condition: Multiple paths with different delays (e.g., in ripple counters).
2. Glitches: Short unwanted pulses due to propagation delay mismatches.
3. Setup/Hold Violations: Data not stable when clocked (causes metastability).

Example: Glitch in a Combinational Circuit

Solutions:

• Use synchronous designs (avoid ripple counters).
• Add delay elements or hazard-free logic.
• Use master-slave flip-flops for edge-triggering.

In the Real World

1. Khalti Payment System

   • FSM Application: The transaction state machine manages:
     • Idle → Processing (on user input).
     • Processing → Complete (on bank confirmation).
     • Complete → Idle (after receipt).
   • Flip-Flops: Used in microcontroller registers to store transaction status.

2. Ncell’s Call Routing

   • Sequential Circuit: The phone call state machine transitions through:
     • Dialing → Connecting → Active → End.
   • Counters: Used in call duration timers (e.g., prepaid call minutes).

3. Daraz Order Fulfillment

   • Registers: Store order IDs in temporary buffers during processing.
   • Counters: Track inventory levels in real-time (e.g., "Only 3 left in stock").

4. NTC Traffic Light Control

   • Moore FSM: Manages Red → Green → Yellow cycles with fixed timers.
   • Flip-Flops: Store the current light state (Red/Green/Yellow).

5. Bank Loan Interest Calculation (Nepal Bank)

   • Sequential Logic: The loan processing system uses FSMs to:
     • Apply → Verify → Approve/Reject → Disburse.
   • Registers: Store customer data (name, loan amount, interest rate).

Practical Example: Traffic Light Controller (Full Design)

Problem: Design a 3-state traffic light controller (Red, Green, Yellow) with:

• Red: 30 sec → Green: 20 sec → Yellow: 5 sec → Repeat.
• Use JK flip-flops and a 555 timer IC for timing.

Solution:

1. State Diagram:

   stateDiagram-v2
       [*] --> Red
       Red --> Green: Timer=30s
       Green --> Yellow: Timer=20s
       Yellow --> Red: Timer=5s

2. State Assignment:

   State	Q2 Q1 Q0
   Red	0 0 0
   Green	0 0 1
   Yellow	0 1 0

3. Excitation Table (for JK flip-flops):

   Present State	Next State	J2 K2	J1 K1	J0 K0
   000 (Red)	001 (Green)	0 1	0 1	1 1
   001 (Green)	010 (Yellow)	0 1	1 1	0 1
   010 (Yellow)	000 (Red)	0 1	0 1	0 1

4. Circuit Implementation:
   • Use 3 JK flip-flops + AND/OR gates for control.
   • 555 Timer generates clock pulses (e.g., 1 pulse per second).

Exam Tip

1. Understand Flip-Flop Behavior:

   • Know D, JK, T, SR flip-flops and their characteristic equations.
   • Always draw timing diagrams for sequential circuits (examiners love this!).

2. FSM Design Steps:

   • State diagram → State reduction → State assignment → Excitation table → Logic equations.
   • Moore vs. Mealy: Identify which is used in the question.

3. Counters:

   • Ripple vs. Synchronous: Know when to use each (speed vs. complexity).
   • Up/down counters: Be able to design both.

4. Timing Hazards:

   • Glitches and race conditions are common exam questions. Explain how to avoid them (e.g., using synchronous design).

5. Real-World Applications:

   • Traffic lights, vending machines, CPUs are classic examples. Relate theory to these in answers.

6. Shortcut for Excitation Tables:

   • For JK flip-flops, use: $$J=Q^{\prime }\cdot \text{Next State},K=Q\cdot {\text{Next State}}^{\prime }$$
   • For D flip-flops, $D=\text{Next State}$.

7. Practical Exam Questions:

   • Design a 4-bit counter (ripple or synchronous).
   • Implement a binary sequence detector (e.g., "110").
   • Analyze a given timing diagram (identify glitches, races).

Final Note: Sequential circuits are everywhere in digital systems. Master flip-flops, counters, and FSMs, and you’ll ace the exam—and understand how CPUs, smartphones, and even traffic lights work!