PLDs, Encoders, Decoders: Design & Applications

TAKEAWAYS:

• PLDs (PROM, PLA, PAL, FPGA) are programmable chips that replace discrete logic gates, reducing circuit complexity and cost.
• Encoders convert multiple input lines into a single output code (e.g., binary, BCD), while decoders do the reverse (e.g., demultiplexing).
• Priority encoders resolve conflicts in multi-input scenarios (e.g., keyboard scanning), and multiplexers act as data selectors.
• FPGAs (Field-Programmable Gate Arrays) enable reconfigurable hardware for prototyping and high-speed applications.
• Decoder applications include memory addressing, 7-segment displays, and traffic light control systems.
• Exam focus: Design circuits using PLDs, analyze encoder/decoder truth tables, and compare PLD types.

1. Programmable Logic Devices (PLDs): Overview and Types

PLDs are integrated circuits designed to replace discrete logic gates, offering flexibility, reduced size, and lower power consumption. They are programmed to implement custom logic functions, making them ideal for prototyping and mass production.

Types of PLDs

PLDs are classified based on their architecture and programmability:

How PLDs Work

PLDs use AND-OR arrays to implement Boolean functions. The AND-plane generates product terms (minterms), while the OR-plane combines them to form the final output.

Advantages and Disadvantages of PLDs

2. Encoders: Converting Inputs to Codes

An encoder is a combinational circuit that converts multiple input lines into a single output code (binary, BCD, etc.). It reduces the number of wires needed for communication.

Types of Encoders

1. Binary Encoder: Converts $2^n$ inputs into $n$-bit binary output.
   • Example: 8-to-3 line encoder (8 inputs → 3-bit binary).
2. Priority Encoder: Resolves conflicts by giving priority to higher inputs (e.g., keyboard scanning).
3. BCD Encoder: Encodes decimal digits (0-9) into 4-bit BCD.

Binary Encoder Example: 4-to-2 Line Encoder

Truth Table:

Logic Expression: $$Y_1=\overline{I_0}\cdot I_2+I_0\cdot I_3$$ $$Y_0=\overline{I_0}\cdot \overline{I_1}\cdot I_3+I_0\cdot \overline{I_1}\cdot \overline{I_2}$$

Circuit Diagram:

Real-World Example:

• Keyboard Scanning: A priority encoder in a computer keyboard detects which key is pressed first (highest priority) and sends the corresponding binary code to the CPU.
• Traffic Light Control: Encoders convert sensor inputs (e.g., vehicle presence) into binary codes for processing by a microcontroller.

3. Decoders: Converting Codes to Outputs

A decoder is the inverse of an encoder: it converts a single input code into multiple output lines. Common types include:

• Binary Decoder (e.g., 2-to-4 line decoder).
• BCD-to-7-Segment Decoder (for displays).
• Demultiplexer (data routing).

Binary Decoder Example: 2-to-4 Line Decoder

Truth Table:

Logic Expression: $$Y_0=\overline{A_1}\cdot \overline{A_0}$$ $$Y_1=\overline{A_1}\cdot A_0$$ $$Y_2=A_1\cdot \overline{A_0}$$ $$Y_3=A_1\cdot A_0$$

Circuit Diagram:

Real-World Example:

• Memory Addressing: A decoder in a computer’s memory unit selects specific RAM/ROM chips based on binary addresses.
• 7-Segment Displays: A BCD-to-7-segment decoder (e.g., 7447 IC) drives LED segments to display digits (0-9).

4. Multiplexers (MUX) and Demultiplexers (DEMUX)

While not strictly PLDs, multiplexers and demultiplexers are closely related to encoders/decoders.

Multiplexer (MUX)

A multiplexer selects one of many input lines and forwards it to a single output line based on select inputs.

• Example: 4-to-1 MUX with select lines $S_1,S_0$.

Truth Table:

Logic Expression: $$Y=\overline{S_1}\cdot \overline{S_0}\cdot I_0+\overline{S_1}\cdot S_0\cdot I_1+S_1\cdot \overline{S_0}\cdot I_2+S_1\cdot S_0\cdot I_3$$

Real-World Example:

• Data Bus Selection: In a computer, a MUX selects data from multiple sources (CPU, RAM, I/O) to send to the bus.
• Pathao Ride Allocation: A MUX-like system routes passenger requests to available drivers based on priority (e.g., nearest driver).

Demultiplexer (DEMUX)

A demultiplexer is the reverse of a MUX: it takes a single input and routes it to one of many output lines based on select inputs.

• Example: 1-to-4 DEMUX.

Truth Table:

Real-World Example:

• Traffic Signal Control: A DEMUX routes a single control signal to different traffic lights based on time slots.
• NTC Electricity Billing: A DEMUX in a smart meter routes power consumption data to different household circuits for monitoring.

5. Field-Programmable Gate Arrays (FPGAs)

FPGAs are the most advanced PLDs, consisting of:

• Configurable Logic Blocks (CLBs): Implement logic functions.
• Input/Output Blocks (IOBs): Interface with external devices.
• Programmable Interconnects: Route signals between CLBs.

FPGA Applications

1. Prototyping: Rapid testing of digital designs before ASIC fabrication.
2. High-Speed Computing: Used in routers, AI accelerators (e.g., Google’s TPUs).
3. Custom Logic: Implementing algorithms like FFT, encryption (AES), or neural networks.

Worked Example: FPGA-Based Traffic Light Controller

• Inputs: Car sensors (4 lanes), pedestrian button.
• Logic: Priority encoder for vehicle lanes, timer for pedestrian crossing.
• Outputs: Control signals for red/green LEDs.
• FPGA Implementation:
  • Use CLBs for priority encoding and timing logic.
  • IOBs connect to sensors and LEDs.

6. Encoder-Decoder Combinations

Encoders and decoders are often used together for data conversion and control.

Example: Keyboard Interface

1. Encoder: Detects which key is pressed (priority encoder).
2. Decoder: Converts the binary code into a display output (e.g., 7-segment LED).

Circuit Flow:

flowchart LR
    A["Keyboard Keys"] --> B["Priority Encoder"]
    B --> C["Microcontroller"]
    C --> D["7-Segment Decoder"]
    D --> E["Display"]

Real-World Example:

• eSewa Payment Terminal: Encodes user input (e.g., PIN) and decodes transaction data for display.
• Khalti QR Scanner: Uses decoders to interpret QR codes and encoders to send transaction requests.

In the Real World

1. Nepalese Banks (e.g., NMB, Global IME): Use PALs in ATMs to decode card swipes and encode transaction data for secure processing.
2. Daraz Order Fulfillment: A priority encoder in the warehouse management system assigns the highest-priority order to the nearest robot for picking.
3. NTC Smart Meters: Decoders interpret binary signals from sensors to display electricity consumption in households.
4. Pathao Driver App: Multiplexers route passenger requests to available drivers based on location (nearest first).
5. NEPSE Stock Ticker: FPGAs in trading terminals process high-speed buy/sell orders with low latency.

Exam Tip

1. Design Questions:
   • For PLDs, show the AND-OR array structure and derive the logic equations.
   • For encoders/decoders, draw the circuit and verify with truth tables.
2. Short Answer:
   • Differentiate between PLA/PAL (programmable planes) and FPGA (reconfigurable).
   • Explain how a priority encoder resolves conflicts (e.g., keyboard input).
3. Numerical Problems:
   • Given a truth table, design a decoder or encoder circuit.
   • Simplify a PLD-based design using Karnaugh maps (from Unit 8).
4. Applications:
   • Relate decoders to memory addressing or 7-segment displays.
   • Link FPGAs to real-world systems (e.g., AI, telecommunications).
5. Common Pitfalls:
   • Forgetting don’t-care conditions in encoder/decoder designs.
   • Mislabeling inputs/outputs in MUX/DEMUX circuits.
   • Overlooking priority logic in encoders (e.g., keyboard scanning).

Key Formulae to Remember:

• Decoder Output: $Y_i=\overline{A_{n-1}}\cdot \overline{A_{n-2}}\cdot \dots \cdot A_0$ (for binary decoder).
• Encoder Priority: Highest input line takes precedence (e.g., $I_3$ > $I_2$).
• FPGA Logic: $\text{CLB}=\text{LUT}+\text{Flip-Flop}$ (Look-Up Table + storage).