Interrupts and DMA – Control Flow, Asynchronous Events, Direct Memory Access

1. Interrupt Fundamentals

An interrupt is a hardware or software signal that temporarily halts the normal execution of a program, transfers control to a special routine called an Interrupt Service Routine (ISR), and then resumes the original program.
Interrupts are essential for responsive systems: they enable devices to notify the CPU when they need service (e.g., keyboard input, timer expiry, network packet arrival).

1.1 Interrupt Vector Table

The CPU uses an Interrupt Vector Table (IVT) to locate the ISR for a given interrupt. Each entry contains the address of the ISR.

The table is usually stored in a fixed memory region (e.g., 0x0000–0x03FF in 8086).

1.2 Interrupt Handling Flow

flowchart TD  
    "CPU executing user code" --> "Interrupt request (IRQ) detected"  
    "IRQ detected" --> "CPU pushes PC and SR onto stack"  
    "Stack updated" --> "CPU reads vector address from IVT"  
    "Vector address fetched" --> "CPU jumps to ISR"  
    "ISR executes" --> "ISR may read/write registers"  
    "ISR completes" --> "CPU executes IRET (return from interrupt)"  
    "IRET" --> "CPU restores PC and SR from stack"  
    "CPU resumes user code"

2. Types of Interrupts

2.1 Maskable vs Non‑Maskable

Maskable interrupts can be disabled by setting a mask bit in the interrupt controller or status register. Non‑maskable interrupts bypass the mask and must be serviced immediately, ensuring high‑priority events are handled.

3. Interrupt Controllers

Modern CPUs use an Interrupt Controller (e.g., Intel’s 8259A, ARM’s GIC) to manage multiple IRQ lines, prioritize them, and generate the correct vector.

The controller typically has two stages: interrupt request and interrupt acknowledge. The CPU acknowledges the interrupt, allowing the controller to clear the request flag.

4. Context Switching in Interrupts

During an interrupt, the CPU must preserve the state of the interrupted program. This involves:

1. Saving registers (general‑purpose, program counter, status register) onto the stack or a dedicated context area.
2. Switching to ISR context (loading ISR registers).
3. Restoring registers upon ISR completion.

The amount of context saved depends on the architecture. In 8‑bit microcontrollers, only a few registers are saved; in 32‑bit CPUs, the entire register file may be preserved.

4.1 Worked Example: Timer Interrupt on an 8051

The ISR runs in 12 machine cycles, while the interrupt latency is 12 cycles plus the time to push registers.

5. Direct Memory Access (DMA)

DMA allows peripherals to transfer data directly to/from memory without continuous CPU intervention. The CPU initiates the transfer by programming the DMA controller; the controller then handles the bus cycles.

5.1 DMA Architecture

flowchart TD
  subgraph DMA_Architecture
    CPU["CPU"] -->|"Programs DMA"| DMA["DMA Controller"]
    DMA -->|"Requests bus"| MEM["Memory"]
    DMA -->|"Reads/Writes"| PER["Peripheral"]
    MEM -->|"Data transfer"| DMA
    PER -->|"Data transfer"| DMA
  end
  CPU -->|"Handles exceptions"| DMA

The DMA controller has:

• Source address (peripheral or memory)
• Destination address (memory or peripheral)
• Transfer size
• Control registers (mode, priority)

5.2 DMA Transfer Sequence

sequenceDiagram  
    participant CPU  
    participant DMA  
    participant MEM  
    participant PERIPH  
    CPU->>DMA: Program transfer (src, dst, size)  
    DMA->>MEM: Request bus access  
    MEM->>DMA: Grant bus access  
    DMA->>PERIPH: Read data  
    DMA->>MEM: Write data  
    loop for each word  
        DMA->>PERIPH: Read next word  
        DMA->>MEM: Write next word  
    end  
    DMA->>CPU: Interrupt (transfer complete)

The CPU can perform other tasks while DMA completes the transfer, improving overall throughput.

5.3 Advantages & Disadvantages

6. Interrupt Priorities and Nesting

Interrupt controllers often support priority levels. Higher priority interrupts can pre‑empt lower priority ones (nesting). The CPU must save the context of the lower priority ISR before servicing the higher one.

6.1 Priority Table Example

If a UART interrupt occurs while servicing a timer interrupt, the UART ISR may be queued or pre‑empted based on the controller’s policy.

7. Real‑World Applications

7.1 eSewa – Payment Gateway

eSewa’s backend servers use DMA to transfer large transaction logs from network interfaces to disk storage. By offloading the transfer, the CPU can process new payment requests in real time, reducing latency during peak hours.

7.2 Pathao – Ride‑Sharing App

Pathao’s Android app receives GPS updates via the NMEA serial interface. The GPS module triggers a hardware interrupt each time a new NMEA sentence arrives. The ISR parses the sentence and updates the UI, ensuring the driver’s location is always current.

7.3 Ncell – Mobile Network

Ncell’s base station firmware uses non‑maskable interrupts to handle critical power‑failure signals. When a power‑supply fault is detected, the NMI forces an immediate shutdown sequence, preventing data corruption.

8. In the real world

Worked Example – ATM Cash Withdrawal

1. User inserts card → Card reader triggers hardware interrupt.
2. ISR reads card data, sends it to CPU via DMA (card data block).
3. CPU verifies PIN, initiates transaction.
4. Cash dispenser triggers interrupt when cash is ejected.
5. ISR updates transaction log via DMA to memory.
6. CPU finalizes transaction and prints receipt.

The use of DMA for log updates ensures the CPU can handle multiple concurrent withdrawals without bottleneck.

9. Exam tip

• Understand the flow: Be able to draw the interrupt handling sequence, including context save/restore and vector lookup.
• Know the types: Memorize the differences between maskable, non‑maskable, hardware, and software interrupts.
• Work through a trace: Practice tracing an ISR, including register values and stack changes.
• DMA details: Explain how DMA reduces CPU load and outline the transfer sequence.
• Priority & nesting: Be ready to explain how nested interrupts are handled and why priority matters.

Good luck!