Sequential Logic: Flip-Flops & Counters (12h)

TAKEAWAYS:

• Sequential circuits depend on memory (flip-flops) to store state, unlike combinational circuits.
• JK flip-flops are universal: they can emulate SR, D, and T flip-flops with clever inputs.
• Counters (ripple vs. synchronous) use flip-flops to count pulses; synchronous counters are faster but costlier.
• State diagrams and timing diagrams are mandatory for designing counters—examiners check both.
• BCD counters (e.g., 7-segment displays) require special logic to avoid invalid states (1010–1111).
• Real-world use: Pathao’s ride counters, NTC’s call queues, and Daraz’s order tracking all rely on sequential logic.

1. Introduction to Sequential Logic

Sequential circuits process inputs and depend on their past states (memory). Unlike combinational circuits, their outputs depend on:

• Present inputs and
• Previous outputs (stored in flip-flops).

Key difference:

graph TD
    A["Combinational"] -->|"Output depends on"| B["Present inputs only"]
    C["Sequential"] -->|"Output depends on"| D["Present inputs + Past state"]

Example: A traffic light (sequential) cycles through red → green → yellow, while a half-adder (combinational) adds two bits instantly.

2. Flip-Flops: The Building Blocks

Flip-flops store 1 bit of data and change state based on inputs. Types covered:

• SR Latch (basic, no clock)
• JK Flip-Flop (universal, clocked)
• D Flip-Flop (data latch, used in registers)
• T Flip-Flop (toggle, for counters)

2.1 SR Latch (Basic Memory Element)

A cross-coupled NAND/NAND gate pair stores state until inputs change.

• Inputs:
  • S (Set): Forces output Q=1 when high.
  • R (Reset): Forces Q=0 when high.
• Rules:
  • If S=R=1: Invalid (race condition).
  • If S=R=0: Holds last state (memory).
• Truth Table:

  S	R	Q (next)
  0	0	Q
  0	1	0
  1	0	1
  1	1	X

Real-world use: E-sewa’s "login state" (stores user session until logout).

2.2 JK Flip-Flop (Clocked Universal Flip-Flop)

Adds a clock (CLK) to synchronize state changes, avoiding race conditions.

• Inputs:
  • J, K: Control state change.
  • CLK: Triggers update on rising edge (default).
• Operation:
  • If J=K=1: Toggle (Q ↔ ¬Q).
  • If J=0, K=1: Reset (Q=0).
  • If J=1, K=0: Set (Q=1).
  • If J=K=0: Hold (no change).
• Excitation Table (for design):

  J	K	Qₙ₊₁
  0	0	Qₙ
  0	1	0
  1	0	1
  1	1	¬Qₙ

Worked Example: Design a toggle circuit using a JK flip-flop.

• Logic: Connect J=K=1 (always toggle on CLK).
• Output: Q toggles every clock pulse (like a digital metronome).

2.3 D and T Flip-Flops (Derived from JK)

• D Flip-Flop: Data latch (Qₙ₊₁ = D).
• T Flip-Flop: Toggle (Qₙ₊₁ = ¬Qₙ if T=1).

Comparison Table:

3. Counters: Storing Sequences

Counters use flip-flops to count pulses. Types:

• Ripple Counter (asynchronous)
• Synchronous Counter (all flip-flops clocked together)
• BCD Counter (decade counter, 0–9)

3.1 Ripple Counter (Asynchronous)

Flip-flops trigger one after another (like dominoes).

sequenceDiagram
    participant FF1
    participant FF2
    participant FF3
    participant CLK
    CLK->>FF1: Rising edge
    FF1->>FF2: Toggle (delayed)
    FF2->>FF3: Toggle (delayed)
    note right of FF1: Delayed propagation
    note right of FF3: Asynchronous chaining

• Advantages: Simple, fewer gates.
• Disadvantages: Slow (propagation delay), glitches.
• Example: A 2-bit ripple counter (mod-4):
  • State Table:

    Q₁Q₀	Count
    00	0
    01	1
    10	2
    11	3
    00	4 (reset)

Worked Example: Design a 3-bit ripple counter (mod-8).

• Logic: Chain 3 JK flip-flops with J=K=1 for each.
• State Diagram:

  stateDiagram-v2
      [*] --> 000
      000 --> 001
      001 --> 010
      010 --> 011
      011 --> 100
      100 --> 101
      101 --> 110
      110 --> 111
      111 --> 000

3.2 Synchronous Counter (Parallel Loading)

All flip-flops clock simultaneously, eliminating glitches.

flowchart TD
    CLK -->|"Rising edge"| FF1
    CLK -->|"Rising edge"| FF2
    CLK -->|"Rising edge"| FF3
    FF1 -->|"Q₀"| FF2["J=Q₀, K=1"]
    FF2 -->|"Q₁"| FF3["J=Q₁, K=1"]

• Advantages: Faster, no propagation delay.
• Disadvantages: Complex control logic.
• Example: 2-bit synchronous up counter:
  • Excitation Table:

    Q₁Q₀	J₁K₁	J₀K₀
    00	01	01
    01	01	11
    10	11	01
    11	11	11

Worked Example: Design a MOD-12 synchronous counter (3-bit, 0–11).

• Logic: Use 3 JK FFs with J₁=Q₀Q₁, K₁=Q₁Q₂, etc.
• State Diagram:

  stateDiagram-v2
      [*] --> 000
      000 --> 001
      ... --> 1011
      1011 --> 0000

3.3 BCD Counter (Decade Counter)

Counts 0–9 (4 bits), skipping 1010–1111.

• Key: Add a decoder to disable invalid states.
• Example: 7-segment display driver (used in digital clocks).

  flowchart TD
      BCD_Counter -->|"0-9"| Decoder
      Decoder -->|"Segment a-g"| 7-Segment_Display

Worked Example: Design a BCD to Excess-3 converter (for error detection).

• Truth Table:

  BCD	Excess-3
  0000	0011
  0001	0100
  ...	...
  1001	1100

• Logic: Add 0011 to BCD input (using full-adders).

4. Real-World Applications

In the Real World

1. Pathao’s Ride Counter:

   • Uses synchronous counters to track ride numbers (e.g., "Ride #12345").
   • Idea: Sequential logic stores the count state until reset.

2. NTC’s Call Queue System:

   • Ripple counters manage call numbers (e.g., "Call #42").
   • Idea: Asynchronous counters are simple and cost-effective for high traffic.

3. Daraz’s Order Tracking:

   • BCD counters track order IDs (0001–9999).
   • Idea: Prevents invalid states (e.g., "Order #1010") via decoder logic.

4. Digital Clocks (e.g., Smartwatches):

   • State machines (JK flip-flops) cycle through hours/minutes/seconds.
   • Worked Example: A 60-minute counter uses a mod-60 synchronous counter with a decoder to reset at 60.

5. Exam Tips

1. State Diagrams Are Mandatory:

   • Always draw state diagrams for counters (e.g., mod-4, mod-8, BCD).
   • Label transitions with clock pulses (↑ for rising edge).

2. Timing Diagrams Show Glitches:

   • For ripple counters, show propagation delay between flip-flops.
   • For synchronous counters, all flip-flops change simultaneously.

3. Excitation Tables > Truth Tables:

   • Use JK/D/T excitation tables to derive flip-flop inputs.
   • Example: For a 2-bit up counter, fill the table as shown above.

4. BCD Counters Need Decoders:

   • Always disable invalid states (1010–1111) with a decoder.

5. Universal JK Flip-Flop:

   • Can emulate SR, D, or T flip-flops. Show conversions in exams.

6. Worked Examples > Theory:

   • Design a 2-bit up/down counter or BCD to Gray code converter for full marks.

Final Note: Sequential logic is everywhere—from your phone’s app counters to Nepal’s NEPSE trading systems. Master state diagrams, timing diagrams, and JK flip-flop logic to ace exams!