Shift Registers & Registers: Serial/Parallel Data Handling

TAKEAWAYS:

• Shift registers convert serial-to-parallel or parallel-to-serial data using flip-flops and clock pulses, enabling efficient data transfer in limited-width buses.
• A 4-bit SISO shift register processes 1010 in 4 clock cycles, shifting bits right while loading the first bit into the MSB position.
• Status registers (e.g., in microcontrollers) track CPU flags like carry, zero, or overflow, while data registers temporarily hold operands for ALUs.
• Ring counters use feedback to cycle through states (e.g., 0001 → 0010 → 0100 → 1000 → 0001), useful in LED chasers or sequential testing.
• Parallel-in serial-out (PISO) registers decode addresses to output serial data, critical for sensor data transmission in IoT devices like smart meters.
• Real-world use: eSewa’s transaction queues (FIFO registers), NTC’s router buffers (shift registers), and Daraz’s order processing (serialized data handling).

1. Introduction to Shift Registers

Shift registers are sequential logic circuits that store and transfer binary data one bit at a time using clock pulses. They convert between serial (one bit per clock) and parallel (multiple bits simultaneously) data formats. Key applications include:

• Data buffering (e.g., serial-to-parallel conversion in USB controllers).
• Serial communication (e.g., UART in microcontrollers).
• Sequential testing (e.g., ring counters in LED displays).

Types of Shift Registers

Shift registers are classified based on data input/output modes:

1. Serial-In Serial-Out (SISO)
   • Input and output are single-bit serial.
   • Used in data transmission lines (e.g., RS-232).
2. Serial-In Parallel-Out (SIPO)
   • Input is serial, output is parallel.
   • Used in LED drivers or sensor data multiplexing.
3. Parallel-In Serial-Out (PISO)
   • Input is parallel, output is serial.
   • Used in microcontroller data logging.
4. Parallel-In Parallel-Out (PIPO)
   • Input and output are parallel (acts as a latch).
   • Used in data storage (e.g., cache registers).

2. Serial-In Serial-Out (SISO) Shift Register

A 4-bit SISO shift register uses 4 D flip-flops connected in series. The serial input (SI) loads the first bit into the MSB flip-flop, and each clock pulse shifts the data right.

Logic Circuit

flowchart TD
    A["D Flip-Flop 1 (MSB)"] -->|"Q"| B["D Flip-Flop 2"]
    B -->|"Q"| C["D Flip-Flop 3"]
    C -->|"Q"| D["D Flip-Flop 4 (LSB)"]
    D -->|"Q"| E["Serial Output (SO)"]
    A -->|"D"| F["Serial Input (SI)"]
    A -->|"CLK"| B
    B -->|"CLK"| C
    C -->|"CLK"| D

Truth Table

Timing Diagram

Clock pulses (↑) shift bits right. After 4 clocks, 1010 is output serially.

Worked Example: SISO with Input 1010

1. Clock 1: SI = 1 → Q1 = 1, others 0.
   • State: 1 0 0 0 (SO = 0).
2. Clock 2: SI = 0 → Q2 = 1, Q1 = 0.
   • State: 0 1 0 0 (SO = 0).
3. Clock 3: SI = 1 → Q3 = 1, Q2 = 0.
   • State: 0 0 1 0 (SO = 0).
4. Clock 4: SI = 0 → Q4 = 1, Q3 = 0.
   • State: 0 0 0 1 (SO = 0).
5. Clock 5: No new SI → SO = 1 (last bit shifted out).

Output sequence: 1 0 1 0 (serial).

3. Parallel-In Parallel-Out (PIPO) Shift Register

A 4-bit PIPO register loads all 4 bits in parallel and holds them until reset. It is essentially a latch for parallel data.

Logic Circuit

flowchart TD
    A["D Flip-Flop 1 (MSB)"] -->|"Q"| B["D Flip-Flop 2"]
    B -->|"Q"| C["D Flip-Flop 3"]
    C -->|"Q"| D["D Flip-Flop 4 (LSB)"]
    A -->|"D"| E["Parallel Inputs (I1-I4)"]
    A -->|"CLK"| B
    B -->|"CLK"| C
    C -->|"CLK"| D

Truth Table (Load on Rising Edge)

Use Case: Temporary storage of microcontroller instructions or sensor data before processing.

4. Serial-In Parallel-Out (SIPO) Shift Register

Used to convert serial data to parallel (e.g., driving 4 LEDs from a single wire).

Logic Circuit

flowchart TD
    A["D Flip-Flop 1 (MSB)"] -->|"Q"| B["D Flip-Flop 2"]
    B -->|"Q"| C["D Flip-Flop 3"]
    C -->|"Q"| D["D Flip-Flop 4 (LSB)"]
    A -->|"D"| E["Serial Input (SI)"]
    A -->|"CLK"| B
    B -->|"CLK"| C
    C -->|"CLK"| D
    D -->|"Q1"| F["Parallel Output 1"]
    C -->|"Q2"| F
    B -->|"Q3"| F
    A -->|"Q4"| F

Worked Example: SIPO with Input 1010

1. Clock 1: SI = 1 → Q1 = 1, others 0.
   • Output: 1 0 0 0.
2. Clock 2: SI = 0 → Q2 = 1, Q1 = 0.
   • Output: 0 1 0 0.
3. Clock 3: SI = 1 → Q3 = 1, Q2 = 0.
   • Output: 0 0 1 0.
4. Clock 4: SI = 0 → Q4 = 1, Q3 = 0.
   • Output: 0 0 0 1.

Final Output: 0 0 0 1 (after 4 clocks, all bits loaded in parallel).

5. Parallel-In Serial-Out (PISO) Shift Register

Used in microcontroller data transmission (e.g., sending sensor readings serially).

Logic Circuit

flowchart TD
    A["D Flip-Flop 1 (MSB)"] -->|"Q"| B["D Flip-Flop 2"]
    B -->|"Q"| C["D Flip-Flop 3"]
    C -->|"Q"| D["D Flip-Flop 4 (LSB)"]
    A -->|"D"| E["Parallel Inputs (I1-I4)"]
    D -->|"Q"| F["Serial Output (SO)"]
    A -->|"CLK"| B
    B -->|"CLK"| C
    C -->|"CLK"| D

Worked Example: PISO with Input 1100

1. Load: I1=1, I2=1, I3=0, I4=0 → Register holds 1 1 0 0.
2. Clock 1: Shift right → 0 1 1 0 (SO = 0).
3. Clock 2: Shift right → 0 0 1 1 (SO = 0).
4. Clock 3: Shift right → 1 0 0 1 (SO = 1).
5. Clock 4: Shift right → 1 1 0 0 (SO = 1).

Output sequence: 0 0 1 1 (serialized).

6. Registers in Digital Systems

Registers are groups of flip-flops used for temporary data storage. Types include:

A. Status Register

• Stores CPU flags (e.g., carry, zero, overflow).
• Example: 8085 microprocessor status register tracks arithmetic results.

B. Program Counter (PC) Register

• Holds the address of the next instruction.
• Auto-increments after fetching an instruction.

C. Data Register

• Holds operands for ALU operations.
• Example: ARM Cortex-M0 uses R0-R15 as data registers.

7. Ring Counter

A specialized shift register where the output of the last flip-flop feeds back to the input, creating a cyclic pattern.

Logic Circuit (4-bit Ring Counter)

flowchart TD
    A["D Flip-Flop 1"] -->|"Q"| B["D Flip-Flop 2"]
    B -->|"Q"| C["D Flip-Flop 3"]
    C -->|"Q"| D["D Flip-Flop 4"]
    D -->|"Q"| A
    A -->|"D"| E["Feedback from Q4"]

State Diagram

States cycle as 0001 → 0010 → 0100 → 1000 → 0001.

Applications

• LED chasers (sequential lighting).
• Sequential testing (e.g., in microcontroller debugging).

8. Comparison Table: Shift Register Types

9. Real-World Applications

A. eSewa Transaction Processing

• Idea: FIFO (First-In-First-Out) queues (implemented with shift registers) manage transaction orders.
• How: When a user initiates a payment, the transaction ID is serialized into a shift register, then dequeued in order for processing.

B. NTC Router Data Buffers

• Idea: PISO shift registers buffer incoming serial data (e.g., from DSL modems) before converting it to parallel for processing.
• How: The router uses a 48-bit PISO register to hold incoming packets temporarily while waiting for the CPU to read them.

C. Daraz Order Processing

• Idea: Serial-to-parallel conversion (SIPO registers) ensures orders are decompressed from serial communication (e.g., from mobile apps) into parallel data for inventory systems.
• Worked Example:
  • A customer orders Item1, Item2, Item3 via Daraz’s app.
  • The app sends 101 (binary for 5) serially.
  • A SIPO register converts it to parallel: 00000101 (5 in 8-bit).
  • The inventory system reads this in parallel to fetch items.

10. Advantages and Disadvantages

Exam Tip

1. Diagrams are Mandatory:

   • Always draw logic circuits (flip-flop connections) and timing diagrams for shift registers.
   • For SISO/SIPO/PISO, label clock, input, output, and flip-flop states clearly.

2. Trace State Transitions:

   • For questions like "Explain 4-bit SISO with input 1010", show each clock cycle with flip-flop values and output.
   • Example:

     Clock 1: SI=1 → Q1=1, Q2=Q3=Q4=0 (SO=0)
     Clock 2: SI=0 → Q2=1, Q1=0 (SO=0)
     ...
     

3. Compare Register Types:

   • Know when to use SISO (serial comms), SIPO (LED drivers), or PIPO (latches).
   • Example question: "Why is a PISO register used in UART?" → Answer: "To convert parallel data (from CPU) to serial for transmission."

4. Real-World Linkage:

   • Connect concepts to Nepali apps:
     • "How does eSewa handle transaction queues?" → FIFO (shift register-based).
     • "How does Pathao route drivers?" → Priority queues (registers for driver status).

5. Common Pitfalls:

   • Mislabeling flip-flops: Always mark MSB (Q1) to LSB (Qn).
   • Ignoring clock edges: Assume rising edge unless specified.
   • Forgetting initial state: Assume all 0 unless reset is given.

Practice Questions (From Past Exams)

1. Define shift register with its types (2023 PU).

   • Answer: A shift register is a sequential circuit that shifts bits using clock pulses. Types: SISO, SIPO, PISO, PIPO, Ring.

2. Draw a 4-bit SISO shift register and explain its operation with input 1101 (2022 TU).

   • Steps:
     • Draw 4 D flip-flops in series.
     • Show timing diagram with SI=1,1,0,1 and outputs after each clock.

3. Explain Ring Counter with a state diagram (2021 NEB).

   • Answer: A ring counter cycles through states using feedback. For 4 bits:

     0001 → 0010 → 0100 → 1000 → 0001
     

     (Draw the state diagram with arrows.)

4. Short Notes: Status Register (2020 PU).

   • Answer: A status register in a CPU stores flags like:
     • Zero Flag (Z): Set if result is 0.
     • Carry Flag (C): Set if overflow in addition.
     • Used in conditional jumps (e.g., JZ if Z=1).