Special Counters & Ring Counters: MOD-n, Synchronous/Ripple, Johnson/Ring Logic

TAKEAWAYS:

• Learn how MOD-n counters cycle through n states (e.g., MOD-12 for a 12-hour clock) using flip-flops and combinational logic.
• Compare synchronous vs. ripple counters in speed, cost, and state transition timing.
• Understand ring counters (shift-register-based) and Johnson counters (twisted ring) for minimal hardware and unique state sequences.
• Design counters for specific MOD values (e.g., MOD-5, MOD-3) with state diagrams, excitation tables, and timing diagrams.
• Apply counters in real systems: Daraz’s order queues (MOD-1000), NTC’s traffic signal timers (MOD-6), or Ncell’s call forwarding (Johnson counter).
• Master state diagrams, timing traces, and gate-level circuits—critical for exam questions.

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1. Introduction to Special Counters

Counters are sequential circuits that count pulses (clock inputs) and display the count in binary or other formats. Special counters include:

• MOD-n counters: Cycle through n states (e.g., MOD-12 for a 12-hour clock).
• Ring counters: Use a shift register to store a single "1" (active state) and rotate it.
• Johnson counters: A variant of ring counters with twisted feedback for unique state sequences.

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1.1 Why Study Special Counters?

• Efficiency: Some counters (e.g., ring) use fewer flip-flops than standard binary counters.
• Applications: Used in digital clocks, traffic lights, data encoding, and error detection.
• Exam Focus: Designing MOD-n counters and analyzing ring/Johnson counters is a common question.

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2. MOD-n Counters

A MOD-n counter cycles through n states before resetting. For example:

• A MOD-12 counter counts from 0000 to 1011 (binary for 11) and resets to 0000.
• Used in 12-hour digital clocks (e.g., smartwatches) or Daraz’s order processing (MOD-1000 for 1000 pending orders).

2.1 Designing a MOD-12 Synchronous Up Counter

Goal: Design a 4-bit synchronous up counter that counts from 0000 to 1011 (12 states) and resets.

Step 1: State Diagram

A state diagram shows the transition between states. For MOD-12:

```mermaid
stateDiagram-v2
    [*] --> 0000
    0000 --> 0001
    0001 --> 0010
    0010 --> 0011
    0011 --> 0100
    0100 --> 0101
    0101 --> 0110
    0110 --> 0111
    0111 --> 1000
    1000 --> 1001
    1001 --> 1010
    1010 --> 1011
    1011 --> 0000

Step 2: State Transition Table

Note: The excitation table depends on the flip-flop type (JK, T, D). For JK flip-flops:

• J = K = 1 → Toggle (for counting).
• J = 0, K = 1 → Reset (for reset to 0000).

Step 3: Logic Design

Use JK flip-flops with combinational logic to generate the excitation signals. For example:

• For Q3 (MSB), the excitation depends on Q2 Q1 Q0 to detect the reset condition (1011 → 0000).
• The reset condition is Q3 Q2 Q1 Q0 = 1011, so:
  • J3 = Q2' Q1' Q0' (reset to 0 when 1011 is detected).
  • K3 = Q2 Q1 Q0 (toggle on other states).

Circuit Diagram:

```figure
{"type":"circuit","inputs":["CLK"],"gates":[{"id":"f0","type":"JK","in":{"J":"Q0'","K":"Q0","CLK":"CLK"},"outputs":["Q0"]},{"id":"f1","type":"JK","in":{"J":"Q1'","K":"Q1","CLK":"CLK"},"outputs":["Q1"]},{"id":"f2","type":"JK","in":{"J":"Q2'","K":"Q2","CLK":"CLK"},"outputs":["Q2"]},{"id":"f3","type":"JK","in":{"J":"Q3'","K":"Q3","CLK":"CLK"},"outputs":["Q3"]}],"logic":[{"type":"NOT","in":["Q0"],"out":["J0"]},{"type":"AND","in":["Q0","Q1"],"out":["J1"]},{"type":"AND","in":["Q0'","Q1"],"out":["J2"]},{"type":"AND","in":["Q0'","Q1'","Q2"],"out":["J3"]}],"caption":"MOD-12 synchronous up counter circuit with JK flip-flops and combinational logic for state transitions."}

Step 4: Timing Diagram

Shows the output over time for one full cycle:

figure

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2.2 Comparison: Synchronous vs. Ripple Counter

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3. Ring Counters

A ring counter is a shift register where only one flip-flop is "1" at a time, and it rotates through the register. Used for minimal hardware and unique state sequences.

3.1 How a Ring Counter Works

• Initial State: 1000 (only Q0 is 1).
• Operation: On each clock pulse, the 1 shifts right (or left) and wraps around.
• Reset: All flip-flops reset to 0 when the 1 returns to its starting position.

Example: 4-bit Ring Counter

```mermaid
stateDiagram-v2
    [*] --> 1000
    1000 --> 0100
    0100 --> 0010
    0010 --> 0001
    0001 --> 1000

3.1.1 State Transition Table

3.1.2 Circuit Diagram

```mermaid
flowchart LR
    subgraph ShiftRegister ["Shift Register (4-bit)"]
        Q0["Q0"] -->|Shift Right| Q1["Q1"]
        Q1 --> Q2["Q2"]
        Q2 --> Q3["Q3"]
        Q3 -->|Feedback| Q0
    end
    Clock["CLK"] --> Q0 Q1 Q2 Q3

3.1.3 Timing Diagram

figure

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3.2 Advantages and Disadvantages

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4. Johnson Counters

A Johnson counter (or twisted ring counter) is a variation of the ring counter with twisted feedback. It has:

• 2n states (where n = number of flip-flops).
• Unique state sequences (not seen in standard ring counters).

4.1 How a Johnson Counter Works

• Feedback: The complement of the output of the last flip-flop is fed back to the first flip-flop.
• States: Cycles through 2n states before resetting.

Example: 2-bit Johnson Counter

```mermaid
stateDiagram-v2
    [*] --> 00
    00 --> 01
    01 --> 11
    11 --> 10
    10 --> 11
    11 --> 01
    01 --> 00

4.1.1 State Transition Table

4.1.2 Circuit Diagram

```mermaid
flowchart LR
    subgraph JohnsonCounter ["2-bit Johnson Counter"]
        Q0["Q0"] -->|Shift Right| Q1["Q1"]
        Q1 -->|Feedback| NOT["NOT"] --> Q0
    end
    Clock["CLK"] --> Q0 Q1

4.1.3 Timing Diagram

figure

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4.2 Applications of Johnson Counters

• Error detection: Used in data communication (e.g., WhatsApp message integrity).
• Sequential logic: Used in digital clocks (e.g., Ncell’s call forwarding).
• Unique state sequences: Used in traffic light controllers (NTC) for non-repeating patterns.

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5. Real-World Examples

5.1 Daraz’s Order Queue (MOD-1000 Counter)

• Idea: Daraz uses a MOD-1000 counter to track pending orders.
• How: Each order is assigned a unique number from 0000 to 0999 (MOD-1000). When an order is fulfilled, the counter increments and wraps around.
• Circuit: A 10-bit synchronous counter with reset logic to 0000 after 0999.

5.2 NTC Traffic Light Timer (Ring Counter)

• Idea: Traffic lights in Kathmandu use a ring counter to cycle through red, yellow, and green.
• How: A 3-bit ring counter rotates the 1 to change the light color:
  • 100 → Red
  • 010 → Yellow
  • 001 → Green
  • 100 → Repeat
• Circuit: 3 JK flip-flops with shift-right logic.

5.3 Ncell Call Forwarding (Johnson Counter)

• Idea: Ncell’s call forwarding uses a Johnson counter to cycle through different numbers.
• How: The counter cycles through 2n states to forward calls to different numbers in sequence.
• Circuit: 4-bit Johnson counter with twisted feedback.

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6. Exam Tips

1. State Diagrams: Always draw the state diagram for MOD-n counters. Show all transitions clearly.
2. Excitation Tables: For JK/T flip-flops, derive the excitation table carefully. Use Karnaugh maps if needed.
3. Timing Diagrams: Show at least one full cycle in the timing diagram. Label all outputs and clock pulses.
4. Circuit Design: For synchronous counters, include the combinational logic (AND/OR gates) for excitation signals.
5. Ring vs. Johnson: Know the difference in feedback and state sequences. Johnson counters have 2n states.
6. Real-World Tie: Relate counters to real systems (e.g., Daraz’s MOD-1000, NTC’s ring counter). Use these in explanations.

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7. Worked Example: Design a MOD-5 Synchronous Up Counter

Goal: Design a 3-bit synchronous up counter that counts from 000 to 100 (MOD-5).

Step 1: State Diagram

Step 2: State Transition Table

Step 3: Logic Design

• Reset Condition: When Q2 Q1 Q0 = 100, reset to 000.
  • J2 = Q1' Q0' (toggle on 011 → 100).
  • K2 = Q1 Q0 (reset on 100).
• Other Flip-Flops: Toggle on rising edge (JK=1,1).

Circuit:

```mermaid
flowchart LR
    subgraph FlipFlops ["JK Flip-Flops"]
        Q2["Q2"] -->|J2| F2["FF2"]
        Q1["Q1"] -->|J1| F1["FF1"]
        Q0["Q0"] -->|J0| F0["FF0"]
    end
    subgraph Logic ["Combinational Logic"]
        L2["J2 = Q1'Q0'"] --> F2
        L1["J1 = Q0"] --> F1
        L0["J0 = 1"] --> F0
    end
    Clock["CLK"] --> F2 F1 F0

Step 4: Timing Diagram

figure

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8. Summary Table of Counters

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9. Common Exam Questions and Answers

Q1: Compare synchronous and ripple counters.

Answer:

• Synchronous:

  • All flip-flops clocked simultaneously.
  • Faster (no delay propagation).
  • More complex (extra combinational logic).
  • Used in digital clocks (NTC traffic lights).

• Ripple:

  • Clock propagates through flip-flops.
  • Slower (delay accumulates).
  • Simpler (no extra gates).
  • Used in simple timers (Pathao ride counters).

Q2: Design a MOD-3 synchronous counter using T flip-flops.

Answer:

1. State Diagram:

   ```mermaid
   stateDiagram-v2
       [*] --> 00
       00 --> 01
       01 --> 10
       10 --> 00
   

2. Excitation Table:

   Current (Q1 Q0)	Next (Q1 Q0)	T1	T0
   00	01	0	1
   01	10	1	0
   10	00	1	1

3. Logic:
   • T0 = 1 (always toggle).
   • T1 = Q0 (toggle when Q0=1).
4. Circuit:

   ```mermaid
   flowchart LR
       Q0["Q0"] -->|T0=1| F0["T FF0"]
       Q1["Q1"] -->|T1=Q0| F1["T FF1"]
       Clock["CLK"] --> F0 F1
   

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10. Final Exam Tips

1. Draw State Diagrams: Always include a state diagram for MOD-n counters. Label all transitions.
2. Use Excitation Tables: For JK/T flip-flops, derive the excitation table systematically.
3. Show Timing Diagrams: Include at least one full cycle in the timing diagram.
4. Relate to Real Systems: Connect counters to real-world examples (e.g., Daraz’s MOD-1000, NTC’s ring counter).
5. Practice Designs: Work on designing MOD-5, MOD-6, and MOD-12 counters to build confidence.
6. Compare Counters: Know the differences between synchronous, ripple, ring, and Johnson counters.