Programmable Logic Devices (PLDs) & Memory-Based Logic: ROM, PLA, PAL, FPGA

TAKEAWAYS:

• PLDs replace fixed logic circuits with programmable memory or gates, enabling flexible, reusable designs.
• ROM stores truth tables directly, while PLA/PAL use AND-OR arrays for efficient logic minimization.
• FPGAs combine configurable logic blocks (CLBs) and programmable interconnects for high-speed custom circuits.
• Memory-based logic (ROM/PROM/EPROM) maps inputs to outputs via stored data, ideal for lookup tables.
• Race conditions and propagation delays are critical in sequential PLD designs, requiring careful timing analysis.
• Real-world uses include eSewa’s transaction validation (PLA-based logic), Daraz’s order routing (FPGA-based switches), and Ncell’s call processing (ROM-based lookup tables).

1. Introduction to Programmable Logic Devices (PLDs)

PLDs are integrated circuits designed to implement combinational or sequential logic without custom hardware fabrication. They eliminate the need for discrete gates or ICs by using programmable memory or logic arrays. PLDs are classified into two main types:

1. Memory-Based Logic: Uses ROM, PROM, EPROM, or EEPROM to store logic functions.
2. Programmable Gate Arrays: Uses configurable logic blocks (CLBs) and programmable interconnects (FPGAs, CPLDs).

Why Use PLDs?

• Flexibility: Reprogrammable for different logic functions.
• Cost-Effective: Reduces hardware complexity and inventory.
• Compactness: Integrates thousands of gates into a single chip.
• Faster Prototyping: Logic can be updated without redesigning hardware.

2. Memory-Based Logic: ROM, PROM, EPROM, EEPROM

Memory-based logic stores truth tables in memory and uses address decoders to fetch outputs. The key components are:

• Address Inputs (A₀, A₁, ..., Aₙ): Represent binary inputs.
• Memory Cells: Store output values (0 or 1) for each input combination.
• Outputs (F₀, F₁, ..., Fₙ): Fetched from memory based on address inputs.

Types of Memory-Based Logic

How ROM Implements Logic

A 4×4 ROM can implement a 2-input, 2-output logic function. For example:

• Inputs: A₀, A₁ (address lines).
• Outputs: F₀, F₁ (stored in memory).

Example: Implement $F_1=\sum (0,2)$ (output 1 when inputs are 00 or 10).

The memory is programmed as:

Logic Diagram:

Advantages of ROM-Based Logic

• Simple Design: No need for complex gate arrangements.
• Fast Operation: Outputs are fetched directly from memory.
• Ideal for Lookup Tables: Used in code converters (BCD to 7-segment), arithmetic functions, and state machines.

Disadvantages

• Memory Inefficiency: Wastes space if many input combinations produce the same output.
• Fixed Logic: ROM/PROM cannot be reprogrammed (except EPROM/EEPROM).

3. Programmable Logic Arrays (PLA) and Programmable Array Logic (PAL)

PLA and PAL are gate-array-based PLDs that use AND-OR arrays for efficient logic implementation.

Structure of PLA

A PLA consists of:

1. Input Lines: Feed into an AND array.
2. AND Array: Generates product terms (minterms).
3. OR Array: Combines product terms to form sum-of-products (SOP) outputs.

Example: Implement $F=\sum (0,2,5)$ using PLA

1. Minterms: $F=\overline{A}\overline{B}\overline{C}+\overline{A}B\overline{C}+AB\overline{C}$.
2. PLA Programming:
   • AND Array: Programmed to generate $\overline{A}\overline{B}\overline{C}$, $\overline{A}B\overline{C}$, and $AB\overline{C}$.
   • OR Array: Connects these terms to output $F$.

PAL vs. PLA

4. Field-Programmable Gate Arrays (FPGAs)

FPGAs are highly configurable PLDs consisting of:

• Configurable Logic Blocks (CLBs): Implement logic functions (e.g., LUTs, flip-flops).
• Programmable Interconnects: Connect CLBs dynamically.
• Input/Output Blocks (IOBs): Interface with external systems.

flowchart TD
    Input["Inputs"] --> CLB1["CLB
(LUT + FF)"]
    Input --> CLB2["CLB
(LUT + FF)"]
    CLB1 -->|"Configurable"| Interconnect["Programmable Interconnect"]
    CLB2 --> Interconnect
    Interconnect -->|"Dynamic Routing"| Output["Outputs"]
    CLB1 -->|"LUT"| LUT1["4×1 LUT"]
    CLB2 -->|"LUT"| LUT2["4×1 LUT"]
    LUT1 --> Interconnect
    LUT2 --> Interconnect

How FPGAs Work

1. Logic Configuration: CLBs are programmed to implement combinational or sequential logic.
2. Routing: Interconnects are configured to route signals between CLBs.
3. Reconfiguration: FPGAs can be reprogrammed for different tasks (e.g., Daraz’s real-time order processing).

Applications of FPGAs

• High-Speed Data Processing: Used in Ncell’s 5G base stations for signal routing.
• Prototyping: Rapid development of custom digital circuits.
• Embedded Systems: Used in automotive control units and medical devices.

5. Real-World Applications

1. eSewa’s Transaction Validation (PLA-Based Logic)

• Problem: eSewa needs to validate transactions based on user input (amount, PIN, time).
• Solution: A PLA is used to implement a state machine that checks:
  • Valid PIN format.
  • Sufficient balance.
  • Transaction limits.
• Why PLA?: Fast lookup and reprogrammability for security updates.

2. Daraz’s Order Routing (FPGA-Based Switching)

• Problem: Daraz’s servers must route orders to warehouses, delivery partners, and payment gateways in real time.
• Solution: FPGAs implement high-speed packet switching with:
  • Custom routing algorithms (CLBs).
  • Low-latency interconnects for fast order processing.
• Why FPGA?: Handles millions of orders/sec with minimal delay.

3. Ncell’s Call Processing (ROM-Based Lookup)

• Problem: Ncell’s switches must map phone numbers to tower locations for routing.
• Solution: A ROM-based lookup table stores:
  • Area codes → Tower IDs.
  • Emergency numbers → Priority routes.
• Why ROM?: Fast, non-volatile storage for critical routing data.

4. NEPSE Stock Market Data (EEPROM for Reconfigurable Logic)

• Problem: NEPSE’s trading terminals need dynamic logic for:
  • Price updates.
  • Order matching.
  • Security protocols.
• Solution: EEPROM-based PLDs allow:
  • Firmware updates without hardware changes.
  • Reconfigurable trading rules (e.g., circuit breakers).

6. Worked Example: Implementing $F=\sum (0,2,5)$ with ROM and PLA

Using ROM (4×3 ROM)

• Inputs: A, B, C (3 bits).
• Output: F (1 bit).
• Memory Contents:

  ABC	F
  000	1
  001	0
  010	1
  011	0
  100	0
  101	0
  110	1
  111	0

Logic Diagram:

Using PLA

1. Minterms: $F=\overline{A}\overline{B}\overline{C}+\overline{A}B\overline{C}+AB\overline{C}$.
2. AND Array:
   • Programmed to generate $\overline{A}\overline{B}\overline{C}$, $\overline{A}B\overline{C}$, and $AB\overline{C}$.
3. OR Array: Connects these terms to $F$.

PLA Diagram:

flowchart LR
    A["A"] --> AND1["AND Array\n(P1: \overline{A}\overline{B}\overline{C})"]
    A --> AND2["AND Array\n(P2: \overline{A}B\overline{C})"]
    A --> AND3["AND Array\n(P3: AB\overline{C})"]
    B["B"] --> AND1
    B --> AND2
    C["C"] --> AND1
    C --> AND2
    C --> AND3
    AND1 --> OR["OR Array"]
    AND2 --> OR
    AND3 --> OR
    OR --> F["F = P1 + P2 + P3"]

7. Exam Tips

1. Understand the Difference Between ROM, PLA, and PAL:

   • ROM stores predefined outputs; PLA/PAL use programmable arrays.
   • Exam Question: "Design a BCD to Excess-3 converter using ROM." → Use a 4×4 ROM with stored outputs.

2. PLA vs. PAL:

   • PLA has programmable AND and OR arrays; PAL has fixed OR structure.
   • Exam Question: "Why is PLA more flexible than PAL?" → Answer: Both AND and OR arrays are programmable in PLA.

3. FPGA Basics:

   • Know CLBs, interconnects, and IOBs.
   • Exam Question: "How does an FPGA implement a counter?" → Use CLBs configured as flip-flops with programmable interconnects.

4. Real-World Mapping:

   • eSewa → PLA/PAL (transaction validation).
   • Daraz → FPGA (high-speed routing).
   • Ncell → ROM (call routing tables).
   • NEPSE → EEPROM (reconfigurable trading logic).

5. Common Pitfalls:

   • Forgetting to minimize logic before implementing in PLA/PAL (use Karnaugh maps).
   • Confusing synchronous vs. asynchronous PLDs (FPGAs are synchronous; ROM is combinational).
   • Ignoring propagation delays in ripple counters (critical for sequential PLDs).

8. Practice Questions (Exam-Style)

1. Design a 3×8 decoder using ROM. Draw the logic diagram and explain how it maps inputs to outputs.
2. Implement $F=\sum (1,3,4,6)$ using PLA. Show the AND-OR array configuration.
3. Compare FPGA and CPLD. Which is better for high-speed routing (e.g., Daraz’s order system)?
4. Why is EEPROM used in NEPSE’s trading terminals? Explain with an example of reconfigurable logic.
5. Draw the timing diagram of a 4-bit ripple counter implemented in an FPGA. Label setup and hold times.

9. Summary Table: PLD Types

10. Final Notes

• PLDs replace fixed logic with programmable memory or gates, reducing hardware complexity.
• ROM is simplest for lookup tables; PLA/PAL are efficient for minimized logic.
• FPGAs are the most flexible but require advanced tools for configuration.
• Real-world ties:
  • eSewa → PLA/PAL (transaction rules).
  • Daraz → FPGA (order routing).
  • Ncell → ROM (call tables).
  • NEPSE → EEPROM (dynamic trading logic).

Exam Strategy:

• For design questions, always show:
  1. Truth table.
  2. Logic diagram (ROM/PLA/PAL/FPGA blocks).
  3. Step-by-step programming (e.g., "Program the AND array to generate minterms...").
• For comparison questions, use a table (like the one above).
• For real-world questions, name the product and explain the PLD’s role (e.g., "FPGA in Daraz handles 10,000 orders/sec with low latency").