Basic Computer Organization & Instruction Execution: Architecture, Cycles, and Registers

Core Concepts: The Anatomy of a Computer System

A computer system is built around three core components:

1. Central Processing Unit (CPU) – Executes instructions (ALU, CU, registers).
2. Memory Unit – Stores data and instructions (RAM, ROM, cache).
3. Input/Output (I/O) Units – Connects the system to external devices.

These components interact via address and data buses, forming the von Neumann architecture (stored-program concept).

1. Basic Block Diagram of a Microprocessor-Based System

2. Register Organization

Registers are high-speed storage units inside the CPU, used for temporary data/instruction storage. Key registers in a basic system:

Why registers matter?

• Speed: Access time is nanoseconds vs. microseconds for RAM.
• Efficiency: Reduces memory access bottlenecks.

3. Instruction Format

An instruction consists of:

• Opcode (Operation Code): Defines the operation (e.g., ADD, MOV).
• Operands: Data or memory addresses involved.

Example: 8085 Instruction Format

For MVI A, 08H (Move Immediate to Accumulator):

• Opcode: 3EH (hex for "Move Immediate").
• Operand: 08H (data to load).

Worked Example: eSewa Transaction When you pay a bill via eSewa:

1. The PC fetches the ADD instruction (to add your balance to the merchant’s account).
2. The IR holds ADD.
3. The ALU performs the addition using registers (e.g., A for your balance, B for the merchant’s).
4. The result is stored back in memory.

4. Instruction Execution Cycle

Every instruction follows 4 stages:

1. Fetch: Get the instruction from memory using the PC.
2. Decode: Interpret the opcode (e.g., ADD vs. MOV).
3. Execute: Perform the operation (ALU or I/O).
4. Store: Write results back to memory/registers.

Timing Diagram for LDA (Load Accumulator) in SAP-1

Key Signals:

• MAR (Memory Address Register): Holds the address to read/write.
• MBR (Memory Buffer Register): Temporarily stores data from/to memory.

5. RISC vs. CISC: A Comparison

Real-World Tie-In: Pathao’s Ride-Hailing App

• Uses RISC-based ARM processors in smartphones for:
  • Fast GPS coordinate calculations (simple ADD/SUB instructions).
  • Efficient battery usage (low power consumption).
• The server backend (handling millions of requests) might use CISC (Intel Xeon) for complex database queries (e.g., JOIN operations in SQL).

6. Memory Hierarchy in Instruction Execution

The memory hierarchy ensures fast access while balancing cost:

Registers (ns) → Cache (10-100 ns) → Main Memory (100 ns - μs) → Secondary Storage (ms)

How it works during instruction execution:

1. PC fetches the instruction address from cache (if hit) or RAM.
2. If the operand is in registers, it’s used directly.
3. If not, a cache miss triggers a memory access (slower).

7. Control Unit (CU) Role

The CU manages instruction execution by:

• Generating control signals (e.g., MEMREAD, ALUOP).
• Coordinating between CPU, memory, and I/O.
• Implementing hardwired or microprogrammed control.

Microprogrammed Control Example: FETCH Cycle

stateDiagram-v2
    [*] --> Fetch
    Fetch --> LoadPC: "PC → MAR"
    LoadPC --> LoadIR: "Memory → MBR → IR"
    LoadIR --> IncrementPC: "PC ← PC + 1"
    IncrementPC --> [*]

Microinstruction Format:

8. Worked Example: Program to Find the Smallest Element in an Array (8085 Assembly)

Problem: Given an array at memory location 2000H, find the smallest element. Assumptions:

• Array size = 10 bytes.
• B = counter, C = current smallest element.

    MVI B, 10       ; Load array size into B
    LXI H, 2000H    ; Load array start address into HL
    MOV C, M        ; Load first element into C (initial smallest)
LOOP: INX H         ; Move to next element
    MOV A, M        ; Load current element into A
    CMP C           ; Compare A with C
    JNC NEXT        ; If A >= C, skip
    MOV C, A        ; Else, update smallest
NEXT: DCR B         ; Decrement counter
    JNZ LOOP        ; Repeat until B=0
    ; C now holds the smallest element

Execution Trace:

Real-World Link: Daraz’s Inventory System

• Daraz’s backend uses similar loops to:
  1. Scan product prices in a database (array).
  2. Find the minimum price for discounts (like our CMP/JNC logic).
  3. Update the UI in real time.

9. Performance Enhancement: Pipelining

Pipelining overlaps instruction execution stages to increase throughput. 4-Stage Pipeline:

Stage 1: Fetch (PC → IR)
Stage 2: Decode (Opcode → Control Signals)
Stage 3: Execute (ALU/I/O)
Stage 4: Writeback (Store result)

Advantages:

• Higher IPC (Instructions Per Cycle): 1 instruction per clock cycle (theoretical max).
• Used in modern CPUs (e.g., Intel Core i7, ARM Cortex).

Disadvantages:

• Pipeline hazards (data, control, structural).
• Requires stalls or forwarding to resolve dependencies.

Example: Ncell’s Billing System

• Uses pipelining to:
  1. Fetch customer data from a database.
  2. Decode billing rules (e.g., "Apply 10% discount if usage > 5GB").
  3. Execute calculations in parallel.
  4. Writeback the updated bill to the system.

In the Real World

1. eSewa’s Transaction Processing

   • Idea Used: Instruction execution cycle and register organization.
   • How: When you transfer money:
     • The PC fetches ADD instructions to update balances.
     • The ALU uses registers (e.g., A for sender balance, B for receiver balance) to perform arithmetic.
     • Results are stored back in memory (database).

2. Khalti’s Payment Gateway

   • Idea Used: Memory hierarchy and pipelining.
   • How:
     • Cache stores frequently accessed transaction records (e.g., merchant IDs).
     • Pipelining processes multiple transactions concurrently (e.g., Stage 1: Fetch user input; Stage 2: Verify PIN; Stage 3: Deduct amount).

3. NTC’s Network Routing

   • Idea Used: Control unit signals and instruction formats.
   • How:
     • Routers use microprogrammed control to parse packets (like decoding instructions).
     • The Opcode in a packet header determines the routing action (e.g., FORWARD, DROP).

Exam Tip

What Examiners Look For

✅ Diagrams: Always draw:

• Block diagrams (CPU, memory, buses).
• Timing diagrams (for LDA, STA instructions).
• State diagrams (for control unit operations).

✅ Definitions with Examples:

• "The Program Counter holds the address of the next instruction to fetch. For example, in the 8085, it’s a 16-bit register that auto-increments after each fetch."

✅ Comparisons:

• RISC vs. CISC: Use a table with real-world examples (e.g., smartphones vs. PCs).
• Hardwired vs. Microprogrammed Control: Explain trade-offs (speed vs. flexibility).

✅ Worked Examples:

• Trace the execution of an instruction (e.g., MVI A, 08H) step-by-step with register changes.
• Programming questions: Write assembly code for a given task (e.g., array search) and explain the logic.

✅ Memory Hierarchy:

• Explain why cache is faster than RAM (proximity to CPU, smaller size).
• Relate to real systems (e.g., "Nepal Rastra Bank’s servers use multi-level cache to process transactions faster").

❌ Avoid:

• Vague answers like "The CPU executes instructions."
• Forgetting to label diagrams (e.g., "MAR," "MBR").
• Ignoring timing (e.g., "It takes 3 clock cycles" without stating the cycles).

Pro Tip: For 6-mark questions, allocate marks as:

• 2 marks: Definition + diagram.
• 2 marks: Step-by-step explanation (with register/memory states).
• 2 marks: Real-world application or comparison.