SAP-1 Architecture: Design, Registers, Instructions & Execution

TAKEAWAYS:

• SAP-1 is a simplified 8-bit microprocessor architecture used to teach core concepts like registers, ALU, control unit, and memory hierarchy.
• It uses a 16-bit address bus (64KB memory) and a 8-bit data bus, with accumulator-based instructions (unlike modern RISC designs).
• The fetch-decode-execute cycle involves 5 stages: Fetch Opcode, Fetch Operand, Execute, Store Result, and Interrupt Handling.
• SAP-1’s instruction format is 2-byte fixed-length (opcode + operand), unlike variable-length CISC or RISC designs.
• Timing diagrams show how clock signals (T1, T2, etc.) control data flow between registers and memory.
• SAP-1 lacks pipelining (unlike modern CPUs) but demonstrates hardwired control and microprogramming basics.

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1. SAP-1 Computer Architecture Overview

SAP-1 (Simple Arithmetic Processor-1) is a hypothetical 8-bit microprocessor designed for educational purposes to explain:

• Basic computer organization (registers, ALU, control unit, memory).
• Instruction execution cycles (fetch, decode, execute).
• Memory addressing (direct, indirect, immediate).
• Control unit design (hardwired vs. microprogrammed).

Key Components of SAP-1

Real Picture:

Register Organization

SAP-1 has 6 key registers (unlike 8085’s 8 registers):

Why 16-bit PC/MAR?

• SAP-1 supports 64KB memory (2¹⁶ = 65,536 addresses).
• Each memory location holds 8 bits (1 byte).

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2. Instruction Format and Types

SAP-1 uses a fixed-length 2-byte instruction format:

┌─────────────┬─────────────┐
│ Opcode (8)  │ Operand (8) │
└─────────────┴─────────────┘

• Opcode (8 bits): Defines the operation (e.g., LDA, ADD, JMP).
• Operand (8 bits): Specifies the data or memory address.

Instruction Types

Comparison: SAP-1 vs. RISC vs. CISC

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3. Instruction Execution Cycle

SAP-1 executes instructions in 5 stages (simplified from 8085’s 4–7 stages):

1. Fetch Opcode: PC → MAR → Memory → MBR → IR.
2. Fetch Operand: If operand is a memory address, fetch data from memory into MBR.
3. Execute: ALU performs the operation (e.g., ADD, AND).
4. Store Result: Write result back to memory/ACC if needed.
5. Interrupt Handling: Check for pending interrupts (e.g., timer, I/O).

Worked Example: LDA A, 50H Execution

Instruction: Load data from memory location 50H into ACC. Steps:

1. Fetch Opcode:
   • PC = 1000H (address of LDA instruction).
   • 1000H → MAR → Memory → MBR → IR (LDA opcode).
   • PC increments to 1001H.
2. Fetch Operand:
   • 1001H → MAR → Memory → MBR (50H = operand).
3. Execute:
   • MAR = 50H (operand is memory address).
   • 50H → MAR → Memory → MBR (data at 50H).
4. Store Result:
   • MBR → ACC (data loaded into accumulator).
5. Next Instruction:
   • PC increments to 1002H (fetch next instruction).

Timing Diagram for LDA A, 50H:

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4. SAP-1 vs. SAP-2: Key Differences

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5. Memory Hierarchy in SAP-1

SAP-1 demonstrates a 3-level memory hierarchy:

1. Registers (fastest, smallest):
   • ACC, MBR, MAR, PC, IR, SP.
   • Access time: 1 clock cycle.
2. Cache (not explicitly modeled in SAP-1 but implied):
   • In real systems, cache reduces memory access time.
3. Main Memory (RAM):
   • 64KB addressable space.
   • Access time: ~10 clock cycles (simplified for teaching).

Real-World Analogy: eSewa App

• Registers = RAM in your phone (fast access for recent transactions).
• Main Memory = Cloud servers storing all user data (slower but larger).
• Cache = Phone’s CPU cache speeding up frequent payments.

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6. Control Unit Design

SAP-1 uses a hardwired control unit (unlike microprogrammed control in SAP-2).

• Hardwired Control:
  • Logic gates directly generate control signals for each instruction.
  • Pros: Faster, simpler for small instruction sets.
  • Cons: Hard to modify; requires redesign for new instructions.

Example: ADD Instruction Control Signals

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In the Real World

1. Khalti App (Nepal)

   • Idea Used: Instruction Execution Cycle
   • How: When you pay via Khalti, the app sends a request to Khalti’s server (like LDA fetching data). The server processes the payment (like ALU execution) and sends a confirmation (like storing result in ACC). The timing of each step (e.g., loading balance, deducting amount) mirrors SAP-1’s fetch-decode-execute cycle.

2. Pathao Driver App (Nepal)

   • Idea Used: Registers and Memory Hierarchy
   • How: The app uses:
     • Registers = Phone’s CPU cache (storing current ride details like pickup/drop locations).
     • Main Memory = Cloud server storing all driver/rider data (slower but persistent).
     • I/O Ports = GPS module (input) and screen (output), like SAP-1’s IN/OUT instructions.

3. NTC Electricity Billing System

   • Idea Used: Stack Operations (Subroutine Calls)
   • How: When you check your bill online, the system:
     • Pushes your user ID onto the "stack" (like PUSH SP).
     • Executes a subroutine to fetch your consumption data (like CALL instruction).
     • Pops the result (bill amount) into ACC (displayed on screen).

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Exam Tip

1. Draw the Block Diagram: Always sketch SAP-1’s architecture (PC → IR → ALU → Memory) in exams. Label all registers and buses.
2. Trace Instructions Step-by-Step: For questions like "Explain LDA execution," list all 5 stages and show timing signals (T1–T4).
3. Compare SAP-1 vs. SAP-2/RISC/CISC: Use a table to highlight differences in word size, registers, and pipelining.
4. Memorize Key Registers: PC, IR, ACC, MAR, MBR, SP. Know their sizes and roles (e.g., PC is 16-bit, ACC is 8-bit).
5. Timing Diagrams: Practice drawing them for ADD, JMP, or LDA. Focus on when MAR, MBR, and ACC change.
6. Real-World Links: If asked about applications, relate SAP-1 concepts to apps like eSewa (execution cycle), Pathao (registers), or NTC (stack).

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SAP-1’s architecture is implemented in real MPs like the 8085, which sits in a socket like this on a motherboard. (Image: smial (talk), FAL, via Wikimedia Commons)