Input/Output Interfacing & DMA: Controllers, Handshakes, and Direct Memory Access

TAKEAWAYS:

• I/O interfacing enables communication between the CPU and peripherals using controllers, handshakes, and data transfer protocols.
• Polling and interrupt-driven I/O are two fundamental methods for CPU-peripheral communication, each with trade-offs in latency and efficiency.
• DMA controllers bypass the CPU for high-speed data transfers, significantly improving system performance for bulk operations.
• DMA modes (single, burst, cycle-stealing) optimize data transfer based on speed and CPU load requirements.
• Real-world examples include eSewa’s secure transaction processing (using DMA for fast data transfer to/from payment gateways) and Ncell’s network traffic routing (DMA for handling bulk SMS/data packets).

1. Introduction to I/O Interfacing

Why I/O Interfacing?

The CPU cannot directly communicate with peripherals (e.g., keyboards, printers, hard drives) due to differences in:

• Speed: CPU operates at GHz, while peripherals (e.g., a printer) work at kHz.
• Protocol: Peripherals use their own signaling methods (e.g., serial vs. parallel).
• Data Format: CPU uses binary, while peripherals may use analog or encoded signals.

Solution: An I/O Interface acts as a translator between the CPU and peripherals, managing:

• Data transfer timing.
• Signal conversion (digital ↔ analog).
• Error handling (e.g., parity checks).

Types of I/O Interfaces

I/O interfaces can be classified based on:

1. Data Transfer Method:

   • Programmed I/O (Polling): CPU repeatedly checks the status of a peripheral.
   • Interrupt-Driven I/O: Peripheral sends an interrupt signal when ready.
   • DMA (Direct Memory Access): Peripheral transfers data directly to/from memory without CPU intervention.

2. Data Transfer Mode:

   • Synchronous: Data transfer synchronized with a clock signal (e.g., USB).
   • Asynchronous: Data transfer triggered by events (e.g., UART for serial communication).

3. Data Width:

   • Parallel: Multiple bits transferred simultaneously (e.g., IDE hard drives).
   • Serial: One bit at a time (e.g., USB, Ethernet).

Real-World Example: eSewa Transaction Processing

When you pay a bill via eSewa:

1. Your smartphone sends a payment request (serial data over USB/Bluetooth).
2. The eSewa server processes the request using interrupt-driven I/O for real-time updates.
3. For bulk transactions (e.g., during festivals), DMA is used to transfer large datasets (e.g., transaction logs) directly to storage without CPU overhead.

2. I/O Controllers and Handshaking

I/O Controller Functions

An I/O Controller is a hardware/software component that:

• Buffers data between the CPU and peripheral.
• Manages handshaking signals (e.g., READY, ACK, BUSY).
• Handles protocol conversions (e.g., UART ↔ CPU bus).

Example: A USB Controller in your laptop manages data transfer between the CPU and a USB flash drive.

Handshaking Protocols

Handshaking ensures reliable data transfer by exchanging control signals. Two common methods:

A. Polling (Programmed I/O)

• CPU repeatedly checks the status of a peripheral (e.g., "Is the printer ready?").
• Steps:
  1. CPU reads the status register of the peripheral.
  2. If the peripheral is busy, CPU waits (wastes CPU cycles).
  3. If ready, CPU sends/receives data.

Mermaid Diagram: Polling Process

stateDiagram-v2
    [*] --> CPU: Checks Status Register
    CPU --> Peripheral: Is Ready?
    Peripheral --> CPU: No (Busy)
    CPU --> CPU: Waits (Wastes Cycles)
    CPU --> Peripheral: Is Ready?
    Peripheral --> CPU: Yes
    CPU --> Peripheral: Transfers Data
    Peripheral --> CPU: Acknowledges
    CPU --> [*]

Advantages:

• Simple to implement.
• No need for interrupt hardware.

Disadvantages:

• CPU overhead: Wastes cycles waiting for slow peripherals.
• Not scalable: Poor for multiple peripherals.

Real-World Example: NTC Traffic Light Control NTC’s traffic light systems use polling to check sensor inputs (e.g., vehicle presence). The CPU repeatedly checks if a sensor is triggered before changing the light.

B. Interrupt-Driven I/O

• Peripheral sends an interrupt signal when ready.
• CPU pauses current task, executes an Interrupt Service Routine (ISR), then resumes.

Steps:

1. Peripheral sets an interrupt flag.
2. CPU finishes current instruction, saves state, and jumps to ISR.
3. ISR handles data transfer, then CPU returns to previous task.

Mermaid Diagram: Interrupt-Driven I/O

sequenceDiagram
    Peripheral->>CPU: Sets Interrupt Flag
    CPU->>CPU: Finishes Current Instruction
    CPU->>CPU: Saves State (PC, Flags)
    CPU->>ISR: Jumps to Interrupt Service Routine
    ISR->>Peripheral: Reads/Writes Data
    ISR->>CPU: Restores State
    CPU->>CPU: Resumes Normal Operation

Advantages:

• Efficient CPU usage: No wasted cycles waiting.
• Scalable: Handles multiple peripherals.

Disadvantages:

• Complexity: Requires interrupt hardware and ISR management.
• Latency: Small delay due to context switching.

Real-World Example: Pathao Ride Requests When you request a ride on Pathao:

1. Your phone sends a request (via Wi-Fi/4G).
2. The Pathao server uses interrupt-driven I/O to immediately process the request (e.g., matching you with a driver) without waiting for polling cycles.

3. Direct Memory Access (DMA)

What is DMA?

DMA (Direct Memory Access) allows peripherals to transfer data directly to/from memory without CPU intervention. This is critical for high-speed devices like:

• Hard drives.
• Network cards.
• Graphics cards.

Key Idea: The DMA Controller acts as a "middleman" between the peripheral and memory, freeing the CPU for other tasks.

How DMA Works

1. CPU initiates DMA transfer by configuring the DMA Controller with:
   • Source/destination addresses.
   • Transfer count.
   • Read/write mode.
2. Peripheral requests data transfer.
3. DMA Controller takes control of the system bus (CPU temporarily stops).
4. Data is transferred directly to/from memory.
5. DMA Controller signals completion (via interrupt or polling).

Mermaid Diagram: DMA Data Transfer

sequenceDiagram
    CPU->>DMA: Configures Controller (Address, Count)
    Peripheral->>DMA: Requests Transfer
    DMA->>Memory: Takes Bus Control
    Peripheral->>Memory: Data Transferred via DMA
    DMA->>CPU: Signals Completion (Interrupt)
    CPU->>DMA: Resumes Normal Operation

DMA Modes

DMA Controller Components

1. Address Register: Holds memory address for data transfer.
2. Word Count Register: Specifies number of words to transfer.
3. Control Register: Configures transfer mode (read/write, burst/single).
4. Status Register: Indicates transfer completion or errors.
5. Bus Request (DRQ) and Bus Grant (DACK) Lines: Handshake signals for bus control.

Advantages of DMA

• Reduces CPU Load: CPU is free for other tasks during transfers.
• Faster Data Transfer: No CPU involvement in each byte transfer.
• Efficient for Bulk Transfers: Ideal for high-speed peripherals (e.g., SSD drives).

Disadvantages of DMA

• Complex Hardware: Requires DMA controller and additional bus signals.
• Bus Contention: DMA and CPU cannot use the bus simultaneously.
• Security Risks: Malicious DMA could corrupt memory (mitigated by modern systems).

Worked Example: DMA in Ncell Network Traffic

Scenario: Ncell’s base station receives 10,000 SMS messages in a minute. Each SMS is 1KB. Problem: If the CPU handles each transfer via programmed I/O, it would take **10,000 CPU cycles per SMS**, leading to delays. Solution: Use DMA to transfer all SMS data directly to memory in bulk.

Calculation:

• Without DMA: CPU handles 10,000 × 1KB = 10 MB via programmed I/O → High latency.
• With DMA: Burst mode transfers 10 MB in ~1 second (assuming 10 MBps transfer rate).

4. Comparison: Polling vs. Interrupt vs. DMA

5. I/O Ports and Memory-Mapped I/O

I/O Ports

• Peripherals communicate via I/O ports (e.g., 0xFF00 for a printer).
• CPU accesses ports using special instructions (e.g., IN/OUT in x86).

Example: In 8085, OUT 30h sends data to port 30h (e.g., a parallel printer).

Memory-Mapped I/O

• Peripherals appear as memory locations (e.g., 0xFFFF0000 for a GPU).
• CPU reads/writes using standard MOV instructions.

Advantages:

• Simpler programming (no special I/O instructions).
• Unified addressing space.

Disadvantages:

• Wastes memory space (ports use memory addresses).
• Harder to debug (memory conflicts).

Real-World Example: Modern GPUs (e.g., NVIDIA) use memory-mapped I/O for rendering frames directly to video memory.

6. Exam Tip

What Examiners Look For

1. Definitions:

   • Clearly define polling, interrupt, and DMA with one-sentence differences.
   • Example: "Polling wastes CPU cycles, while DMA eliminates CPU involvement entirely."

2. Diagrams:

   • Draw handshake signals (e.g., READY, ACK) for polling/interrupt.
   • Show a DMA transfer sequence with bus arbitration.

3. Real-World Applications:

   • Link concepts to eSewa (DMA for transactions), Ncell (interrupts for SMS), or NTC (polling for traffic lights).
   • Example: "In Pathao’s app, interrupt-driven I/O ensures real-time ride updates without CPU delays."

4. Worked Examples:

   • Calculate CPU cycles saved using DMA vs. polling.
     • Example: "A 10 MB file transfer via polling takes 10,000 CPU cycles per KB. With DMA, it takes 1 cycle per KB → 99.99% reduction."

5. Comparison Tables:

   • Always include a polling vs. interrupt vs. DMA table in your answer.

6. Common Pitfalls:

   • Don’t confuse DMA with cache: DMA transfers data to/from memory, while cache speeds up CPU access.
   • Don’t forget bus arbitration: DMA needs DRQ/DACK signals to use the bus.

Model Answer Structure for Exam Questions

Question: "Explain the role of a DMA controller in data transfer with an example." Answer Structure:

1. Definition: "DMA controller enables peripherals to transfer data directly to/from memory without CPU intervention."
2. Components: List address register, word count register, etc. (with a block diagram).
3. Process: Describe steps with a sequence diagram.
4. Example: "In eSewa, DMA transfers bulk transaction logs to storage during peak hours, reducing CPU load by 80%."
5. Advantages: List 2–3 key benefits (e.g., speed, CPU efficiency).

Past Exam Question Analysis

Question: "What is DMA? Explain the role of DMA controller in data transfer." Expected Answer:

• Definition: "DMA (Direct Memory Access) is a technique where a peripheral transfers data directly to/from memory via a DMA controller, bypassing the CPU."
• Role of DMA Controller:
  • Acts as a bus master (takes control of the system bus).
  • Manages addressing and transfer count.
  • Handles handshaking (DRQ/DACK signals).
• Example: "In a bank’s ATM system, DMA transfers transaction records to the database during off-peak hours, preventing CPU bottlenecks."

In the Real World

1. eSewa Transactions:

   • Idea Used: DMA for bulk data transfer.
   • How: During Diwali sales, eSewa processes thousands of transactions per second. DMA transfers payment data directly to the server’s database, reducing latency by 70% compared to CPU-driven transfers.

2. Ncell Network Traffic:

   • Idea Used: Interrupt-driven I/O for real-time SMS routing.
   • How: When you send an SMS, Ncell’s base station uses interrupts to immediately forward the message to the recipient’s tower without polling delays. This ensures <1 second delivery even during network congestion.

3. Daraz Order Fulfillment:

   • Idea Used: Memory-mapped I/O for warehouse robots.
   • How: Daraz’s automated warehouses use memory-mapped I/O to control robotic arms. The CPU sends commands to "memory locations" corresponding to robot joints, enabling millisecond-precision movements for order picking.

4. Khalti Payment Gateway:

   • Idea Used: Polling for low-latency merchant verification.
   • How: When you pay via Khalti, the system polls the merchant’s server every 50 ms to check if the payment is authorized. While not the fastest method, it ensures no transaction is missed due to interrupt delays.

Key Takeaways for Exam Success

• Memorize the handshake signals (READY, ACK, BUSY, DRQ, DACK).
• Practice drawing:
  • Polling/interrupt state diagrams.
  • DMA sequence diagrams.
• Relate to Nepalese tech: Always use eSewa, Ncell, Daraz, or NTC in examples.
• Calculate savings: For DMA vs. polling, show CPU cycles saved (e.g., "99.9% reduction").