8085 Instruction Set & Addressing Modes: Formats, Types, and Real-World Traces

TAKEAWAYS:

• The 8085 instruction set is divided into 5 types (data transfer, arithmetic, logic, branch, and stack/machine control) with 7 addressing modes to specify operands.
• Instruction format determines opcode length (1–3 bytes) and operand fields, directly impacting execution time (e.g., MVI A, 08H takes 10 T-states vs. ADD B’s 4).
• Addressing modes like direct, register indirect, and immediate enable flexible operand access; HL pair is critical for memory operations.
• Worked examples (e.g., finding the smallest array element) show how to combine instructions and loops, while timing diagrams reveal clock-cycle overheads.
• Real-world applications include Khalti’s payment validation (branch instructions for error handling) and NTC’s traffic light control (timed loops via RST and JMP).
• Exam focus: Trace execution cycles, differentiate modes, and calculate T-states for given instructions.

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1. Instruction Set of 8085: Classification and Formats

The 8085 instruction set is fixed-length (opcodes 1–3 bytes) and categorized into 5 types, each serving distinct functions. The format of an instruction defines how the opcode and operands are encoded, affecting memory usage and execution speed.

1.1 Classification of Instructions

The 8085 instructions are grouped as follows:

Key Point:

• Single-byte opcodes (e.g., MOV B, C) execute faster (4 T-states) than multi-byte ones (e.g., MVI M, 34H takes 10 T-states).
• Accumulator (A) is involved in most arithmetic/logic operations.

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1.2 Instruction Formats

The 8085 uses 3 primary formats:

Visual: Instruction Format Fields

Example: The instruction ADD B has:

• Opcode: 10000010 (8 bits, 82H in hex).
• No operand field (register B is implied).

Worked Example: Timing Calculation Question: How long does MVI A, 08H take at 5 MHz? Solution:

• Clock period = $\frac{1}{5\text{ MHz}}=0.2\mu s$.
• T-states for MVI A, 00H = 7 (from datasheet).
• Execution time = $7\times 0.2\mu s=1.4\mu s$.

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2. Addressing Modes: How Operands Are Specified

Addressing modes determine how the operand is located in memory or registers. The 8085 supports 7 modes:

Comparison Table:

Key Point:

• HL pair is critical for register indirect mode (e.g., MOV A, M reads from [HL]).
• Direct addressing uses 3 bytes (opcode + 16-bit address), slowing execution.

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3. Worked Example: Finding the Smallest Element in an Array

Problem: Write an 8085 program to find the smallest element in an array stored at 2000H (10 bytes). Assume B holds the array size.

Solution:

        LXI H, 2000H   ; Load array start address to HL
        MOV A, M       ; Load first element to A (initial min)
        INR H          ; Move to next element
        MOV C, B       ; Load array size to C (counter)
LOOP:   MOV B, M       ; Load current element to B
        CMP B          ; Compare with A (min)
        JNC NEXT       ; Jump if A ≤ B (no update)
        MOV A, B       ; Else, update min
NEXT:   INR H          ; Move to next element
        DCR C          ; Decrement counter
        JNZ LOOP       ; Repeat until all elements checked
        ; A now holds the smallest element

Trace Execution:

1. Initialization: HL = 2000H, A = [2000H] (first element).
2. Loop:
   • Compare A with [HL].
   • If [HL] < A, update A.
   • Increment HL and decrement counter (C).
3. Termination: After 10 iterations, A contains the smallest value.

Real-World Tie-In: This logic is used in NEPSE’s stock price analysis (finding the lowest price in a day’s trading data) or Khalti’s fraud detection (identifying the smallest transaction amount in a batch).

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4. Instruction Cycle and Timing Diagrams

Every instruction executes in fetch-decode-execute cycles. The timing diagram for LDA 2100H (3-byte instruction) is:

Key Observations:

• Multi-byte instructions require extra fetch cycles.
• Memory access (e.g., LDA) adds latency compared to register ops (ADD B).

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5. In the Real World

1. Khalti’s Payment Validation:

   • Uses conditional jumps (JC/JNC) to check if a transaction amount exceeds limits.
   • Example: CMP A, 50000 followed by JNC REJECT (reject if amount ≥ 50,000).

2. NTC’s Traffic Light Control:

   • Timed loops with DCR and JNZ to cycle lights every 30 seconds.
   • Example:

     MVI C, 30       ; 30-second count
     LOOP: CALL DELAY ; Delay subroutine
           DCR C
           JNZ LOOP
     

3. Daraz’s Order Queue Management:

   • Stack operations (PUSH/POP) prioritize urgent orders.
   • Example: PUSH H saves the current order pointer before processing.

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6. Exam Tip

• Memorize T-states: Know the execution time for common instructions (e.g., MOV = 4, MVI = 7, LDA = 13).
• Trace step-by-step: For programs, show register/memory changes at each step.
• Differentiate modes: In exams, always specify which addressing mode is used (e.g., "direct addressing in STA 3000H").
• Calculate timing: Given a clock frequency, compute execution time (e.g., 5 MHz → 0.2 µs per T-state).

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