8085 Microprocessor: Architecture & Functional Units

TAKEAWAYS:

• The 8085 microprocessor is an 8-bit CPU with 40 pins, organized into functional units (ALU, registers, control unit, and I/O interfaces) that execute instructions via a 5-step fetch-decode-execute cycle.
• Key registers (A, B, C, D, E, H, L, SP, PC, PSW) store data, addresses, and flags, while the ALU performs arithmetic/logic operations and updates flags (Z, S, P, CY, AC).
• The control unit decodes instructions and generates timing/control signals (e.g., HLDA, INTA) to synchronize data transfer with memory/I/O devices.
• System architecture includes a minimal 8085-based system (CPU + memory + I/O) connected via address/data/bus lines, with memory-mapped I/O for peripheral communication.
• Real-world use: The 8085 powers embedded systems (e.g., traffic light controllers, industrial PLCs) and legacy devices (e.g., early calculators, medical equipment).
• Exam focus: Block diagrams (CPU, control unit), register functions, flag meanings, and step-by-step instruction execution traces.

1. Introduction to the 8085 Microprocessor

The 8085 is an 8-bit microprocessor introduced by Intel in 1976, widely used in early computers and embedded systems. It operates on a 5 MHz clock, has 40 pins, and supports 256 bytes of memory directly (via 8-bit address bus). Its architecture is von Neumann (shared memory for data/instructions) and Harvard-like (separate data/address buses for efficiency).

Key Features

• 8-bit data bus: Transfers 8 bits at a time (1 byte).
• 16-bit address bus: Accesses 64 KB of memory (2¹⁶ = 65,536 bytes).
• 5-step instruction cycle:
  1. Fetch (opcode from memory to IR).
  2. Decode (control unit interprets opcode).
  3. Execute (perform operation).
  4. Memory read/write (if needed).
  5. Interrupt acknowledge (if pending).
• Interrupt-driven I/O: Supports 5 maskable (INTR, RST 5.5–7.5) and 1 non-maskable (TRAP) interrupts.

2. Functional Units of the 8085

The 8085’s architecture is divided into 5 main functional units:

A. Arithmetic Logic Unit (ALU)

• Performs arithmetic (add, subtract, increment, decrement) and logic operations (AND, OR, XOR, NOT, compare).
• Flags updated: Zero (Z), Sign (S), Parity (P), Carry (CY), Auxiliary Carry (AC).
• Example: After ADD B (add register B to A), the ALU sets flags based on the result.

stateDiagram-v2
    [*] --> ALU: Input (A, B)
    ALU --> Result: A + B
    ALU --> Flags: Z/S/P/CY/AC
    Result --> [*]

B. Registers

The 8085 has 8 general-purpose registers (16-bit pairs: BC, DE, HL) and special-purpose registers:

C. Control Unit

• Decodes instructions from the Instruction Register (IR).
• Generates timing/control signals (e.g., MEMW, IOR, INTA) to coordinate data flow.
• Two types:
  1. Hardwired Control Unit: Fixed logic for each instruction (faster but inflexible).
  2. Microprogrammed Control Unit: Uses a control store (microprogram) to decode instructions (slower but flexible).

D. I/O and Interrupt System

• I/O Ports: 8085 has 256 I/O ports (addressed via IN/OUT instructions).
• Interrupts:
  • Maskable: INTR (edge-triggered), RST 5.5–7.5 (level-triggered).
  • Non-maskable: TRAP (highest priority, used for critical errors).
  • Interrupt cycle:
    1. CPU finishes current instruction.
    2. Sends INTA (interrupt acknowledge) signal.
    3. Interrupting device sends 8-bit vector (e.g., RST 7.5 jumps to 003CH).

E. System Bus Structure

The 8085 connects to memory/I/O via three buses:

1. Address Bus (16 lines, A0–A15): Outputs memory/I/O addresses.
2. Data Bus (8 lines, D0–D7): Bidirectional (input/output data).
3. Control Bus: Signals like RD (read), WR (write), HLDA (hold acknowledge).

3. 8085 Microprocessor Pin Configuration

The 40-pin DIP package includes:

• Address Bus (A0–A15): 16 lines (A8–A15 multiplexed with data bus).
• Data Bus (D0–D7): 8 lines (bidirectional).
• Control Signals:
  • RD, WR: Memory/I/O read/write.
  • HLDA: Hold acknowledge (for DMA).
  • INTA: Interrupt acknowledge.
  • RESET IN/OUT: Initializes CPU.
  • TRAP: Non-maskable interrupt.
  • SID/SOD: Serial I/O (for peripheral communication).
• Power Supply: Vcc (+5V), GND.

4. Minimal 8085-Based System

A basic system requires:

1. 8085 CPU
2. Memory:
   • ROM (e.g., 2716 EPROM, 2 KB) for program storage.
   • RAM (e.g., 6116 SRAM, 2 KB) for data.
3. I/O Devices: Keyboard, display, or parallel ports.
4. Support Chips:
   • Clock Generator (e.g., 8224) for 5 MHz clock.
   • System Controller (e.g., 8228) for status signals.
   • Address Latch (e.g., 74LS373) to hold high-order address bits.

5. Real-World Applications of 8085

In the Real World

1. Traffic Light Controllers

   • How it uses 8085: The 8085’s timer/counter and I/O ports control LED sequences and sensors. A program reads input from sensors (e.g., IN 0x01) and toggles outputs (OUT 0x02) to change light colors.
   • Example: Kathmandu’s smart traffic systems (e.g., at Thapathali) use 8085-based PLCs to optimize flow based on vehicle density.

2. Medical Equipment (e.g., ECG Machines)

   • How it uses 8085: The ALU processes analog signals from sensors, while interrupts handle emergency alerts (e.g., TRAP for heart rate anomalies). The stack stores patient data temporarily.
   • Example: Nepal’s rural clinics use 8085-based ECG monitors (e.g., models from Siemens or Philips legacy systems) for real-time heart monitoring.

3. Embedded Calculators (e.g., Scientific Calculators)

   • How it uses 8085: The instruction set (e.g., DAD H for 16-bit add) handles complex math, while flags manage overflow. The serial I/O (SID/SOD) displays results on an LCD.
   • Example: Old Casio fx-3600P calculators (still used in schools) run on an 8085-like core for arithmetic operations.

6. Worked Example: Finding the Smallest Element in an Array

Problem: Write an 8085 assembly program to find the smallest element in an array stored in memory (starting at 2000H), with length stored at 20FFH.

Solution

        MVI   C, 00H       ; Initialize counter C = 0
        LXI   H, 2000H     ; HL = start of array
        MOV   A, M         ; Load first element to A (assume smallest)
LOOP:   INR   C           ; Increment counter
        MOV   B, C        ; Copy counter to B
        CPI   0FFH        ; Compare B with array length (at 20FFH)
        JZ    DONE         ; If equal, exit
        INX   H           ; Move to next element
        CMP   M           ; Compare A with current element
        JNC   LOOP        ; If A <= M, skip
        MOV   A, M        ; Else, update A with new smallest
        JMP   LOOP
DONE:   ; A now holds the smallest element
        HLT

Explanation

1. Initialization: Load the first array element into A (assumed smallest).
2. Loop:
   • Increment counter C and compare with array length (20FFH).
   • Move to next element (INX H).
   • Compare A with current element (CMP M).
   • Update A if a smaller element is found (JNC skips if A <= M).
3. Termination: HLT halts the CPU with the result in A.

Real-World Tie-In: This logic is used in Daraz’s order processing system to find the lowest-priced item in a product category. The 8085’s looping and comparison instructions mirror how modern systems filter data, though scaled up with databases.

7. Exam Tip: How to Score Full Marks

1. Block Diagrams:

   • Must include: All functional units (ALU, registers, control unit, I/O).
   • Label clearly: Use arrows for data flow (e.g., PC → MAR → Memory).
   • Example: For the control unit, show IR → Decoder → Control Signals.

2. Register Functions:

   • Memorize: Size, purpose, and example instructions for each register (e.g., SP for PUSH/POP, PC for JMP).
   • Flag meanings: Write a short note on when each flag (Z, S, P, CY, AC) is set.

3. Instruction Execution:

   • Trace step-by-step: For ADD B, show:
     1. Fetch opcode from PC.
     2. Decode to ADD instruction.
     3. ALU adds A and B, updates flags.
   • Use timing diagrams if asked (e.g., T1–T5 states for fetch cycle).

4. Minimal System:

   • Draw and explain: CPU + memory + I/O + support chips (8224, 8228).
   • Addressing: Show how A0–A7 (low byte) and A8–A15 (high byte) are latched.

5. Common Pitfalls:

   • Don’t forget: The multiplexed address/data bus (A0–A7 share pins with D0–D7).
   • Interrupts: Differentiate between maskable (INTR) and non-maskable (TRAP).
   • Flags: Z is set if result is zero; CY if carry occurs.

8. Past Exam Questions and Solutions

Q1: Draw the block diagram of the 8085 microprocessor and explain its functional units.

Solution:

Explanation:

• Control Unit: Decodes instructions and generates timing signals.
• ALU: Performs arithmetic/logic operations (e.g., ADD, AND).
• Registers: Store operands (A, B, C, etc.) and addresses (PC, SP).
• Memory Interface: Connects to ROM/RAM via address/data buses.
• I/O Interface: Handles data transfer with peripherals (e.g., IN, OUT).

Q2: Explain the basic architecture of an 8085-based system.

Solution: A minimal system includes:

1. CPU (8085): Executes instructions.
2. Memory:
   • ROM (2716): Stores firmware (e.g., bootloader).
   • RAM (6116): Temporary data storage.
3. Support Chips:
   • 8224 Clock Generator: Provides 5 MHz clock.
   • 8228 System Controller: Manages status signals (RD, WR).
   • 74LS373 Address Latch: Holds high-order address bits (A8–A15).
4. I/O Devices: Keyboard, display, or parallel ports.

9. Summary Table: 8085 Functional Units