Microprocessors, Architecture & Computer Systems

TAKEAWAYS:

• A microprocessor is the brain of a computer, executing instructions fetched from memory and performing arithmetic/logic operations.
• Computer architecture defines how components (CPU, memory, I/O) interact, with von Neumann architecture as the standard model.
• Memory hierarchy (registers → cache → RAM → disk) balances speed and cost, with each level closer to the CPU being faster but smaller.
• SAP-1 is a simple single-address architecture used to illustrate basic instruction execution and fetch-decode-execute cycles.
• Modern microprocessors (e.g., 8085) use registers, ALU, CU, and memory to execute complex tasks efficiently.
• RISC vs. CISC trade offs (instruction set complexity vs. performance) shape how microprocessors are designed today.

1. Introduction to Microprocessors

A microprocessor is an integrated circuit (IC) that contains the Central Processing Unit (CPU) and performs computations by executing instructions stored in memory. It is the core component of any digital system, from smartphones to supercomputers.

Key Components of a Microprocessor

Every microprocessor consists of:

• Arithmetic Logic Unit (ALU): Performs arithmetic (addition, subtraction) and logic operations (AND, OR, NOT).
• Control Unit (CU): Manages instruction execution by decoding and executing instructions.
• Registers: Small, fast storage locations inside the CPU (e.g., Accumulator (ACC), Program Counter (PC), Stack Pointer (SP)).
• Memory Interface: Connects the CPU to external memory (RAM, ROM).
• Input/Output (I/O) Interface: Handles communication with peripherals (keyboard, display, etc.).

flowchart TD
    A["Microprocessor"] --> B["ALU"]
    A --> C["Control Unit"]
    A --> D["Registers"]
    A --> E["Memory Interface"]
    A --> F["I/O Interface"]
    B -->|"Performs"| G["Arithmetic/Logic"]
    C -->|"Decodes"| H["Instructions"]
    D -->|"Temporary"| I["Data Storage"]
    E -->|"Connects"| J["RAM/ROM"]
    F -->|"Handles"| K["Peripherals"]

How a Microprocessor Works

1. Fetch: The Program Counter (PC) holds the address of the next instruction. The CU fetches the instruction from memory.
2. Decode: The CU interprets the instruction (e.g., ADD, JMP).
3. Execute: The ALU performs the operation, and results are stored in registers or memory.
4. Store: If needed, results are written back to memory.

Example: Fetching and executing LDA 2000H (Load Accumulator from memory address 2000H):

1. PC = 2000H → Instruction fetched.
2. CU decodes LDA → Loads data from 2000H into ACC.
3. Result stored in ACC.

2. Computer Architecture: Von Neumann vs. Harvard

flowchart TD
    subgraph VonNeumann
        A["CPU"]
        B["Memory"]
        C["I/O"]
        A -->|"Shared Bus"| B
        A -->|"Shared Bus"| C
        B -->|"Data/Instructions"| A
    end
    subgraph Harvard
        D["CPU"]
        E["Instruction Memory"]
        F["Data Memory"]
        G["I/O"]
        D -->|"Dedicated Bus"| E
        D -->|"Dedicated Bus"| F
        D -->|"Separate Bus"| G
    end
    VonNeumann -->|"Standard Model"| Harvard
    caption "Von Neumann (left) vs. Harvard (right) memory architectures"

Von Neumann Architecture (Stored-Program Model)

• Single memory bus for data and instructions.
• Sequential execution: Instructions are fetched one by one.
• Used in 8085, SAP-1, and most modern CPUs.

flowchart TD
    A["CPU"] --> B["Control Unit"]
    A --> C["ALU"]
    B --> D["Memory"]
    C --> D
    D --> E["I/O"]
    D --> F["Input"]
    D --> G["Output"]

Harvard Architecture

• Separate memory buses for data and instructions (faster for embedded systems).
• Used in some DSPs (Digital Signal Processors) and older calculators.

Comparison Table

3. Memory Hierarchy in Computers

Memory hierarchy organizes storage levels by speed, cost, and capacity to optimize performance.

figure: Memory Hierarchy

Registers (Fastest, Smallest)
       │
       ▼
Cache (L1, L2, L3)
       │
       ▼
RAM (Main Memory)
       │
       ▼
Disk (Slowest, Largest)

Levels of Memory Hierarchy

Example: When you open a Daraz app, data is first loaded from SSD (disk) → RAM → L3 Cache → L1 Cache → Registers for fast processing.

4. Basic Computer Architecture (SAP-1)

SAP-1 (Simple Address Processor) is a single-address architecture used to explain basic instruction execution.

Block Diagram of SAP-1

figure: SAP-1 Block Diagram

┌───────────────────────────────┐
│         CPU                   │
│  ┌─────────┐    ┌─────────┐   │
│  │  ALU    │    │  CU     │   │
│  └─────────┘    └─────────┘   │
│       │                  │    │
│       ▼                  ▼    │
│  ┌───────────────────────┐    │
│  │   Registers (ACC, PC) │    │
│  └───────────────────────┘    │
│       │                  │    │
│       ▼                  ▼    │
│  ┌───────────────────────┐    │
│  │        Memory         │    │
│  └───────────────────────┘    │
└───────────────────────────────┘

Registers in SAP-1

Instruction Format

SAP-1 uses a single-address format:

figure: SAP-1 Instruction Format

┌───────────────────────────────┐
│  8-bit Opcode (Operation)     │
└───────────────────────────────┘
┌───────────────────────────────┐
│  8-bit Address (Memory Address)│
└───────────────────────────────┘

Total: 16-bit instruction

Example Instruction: LDA 2000H

• Opcode: 00000001 (Load Accumulator)
• Address: 2000H (Memory location)

5. Fetch-Decode-Execute Cycle (SAP-1 Example)

Let’s trace the execution of LDA 2000H:

sequenceDiagram
    participant CPU
    participant Memory
    participant ALU
    
    CPU->>Memory: Fetch (PC=1000H)
    Memory-->>CPU: Returns LDA 2000H
    CPU->>CPU: Decode (LDA)
    CPU->>Memory: MAR=2000H
    Memory-->>CPU: Data from 2000H
    CPU->>ALU: Load ACC
    ALU-->>CPU: ACC=Data
    caption "SAP-1 execution of `LDA 2000H` (step-by-step)"

1. Fetch:

   • PC = 1000H (holds address of LDA 2000H).
   • Fetch instruction from 1000H → LDA 2000H stored in IR.
   • PC increments to 1001H.

2. Decode:

   • CU reads LDA opcode → "Load data from memory into ACC."

3. Execute:

   • MAR = 2000H (address part of instruction).
   • Data from 2000H loaded into MBR → ACC.
   • PC = 1001H (next instruction).

Timing Diagram:

figure: LDA Instruction Timing

T0: Fetch IR ← [1000H]
T1: MAR ← 2000H
T2: MBR ← [2000H] → ACC
T3: PC ← 1001H

6. RISC vs. CISC: Key Differences

Example:

• RISC: ADD R1, R2, R3 (adds R2 + R3 → R1).
• CISC: ADD [R1], [R2], [R3] (adds memory locations).

In the real world

1. eSewa & Khalti (Mobile Payments)

   • Idea: Microprocessor-based security in payment processing.
   • How: When you pay via eSewa, the microprocessor in your phone (e.g., ARM-based CPU) encrypts transaction data before sending it to the server. The control unit ensures only valid instructions (e.g., AES encryption) are executed to prevent fraud.

2. Daraz (E-commerce Order Processing)

   • Idea: Memory hierarchy in order fulfillment.
   • How: When you order a product, Daraz’s servers use fast RAM (L3 cache) to process your request quickly. If the product is out of stock, the CPU (8085-like architecture) checks the database (disk) via memory management units (MMU) to update inventory in real time.

3. Pathao (Ride-Hailing Dispatch System)

   • Idea: Instruction execution in real-time routing.
   • How: Pathao’s backend uses microprocessors in servers to execute instructions like:
     • LDA driver_location (load driver’s GPS data).
     • CMP passenger_location (compare with passenger’s location).
     • JMP assign_driver (if close, assign ride). The pipelining technique (Unit 9) allows multiple drivers to be checked simultaneously for faster matching.

Exam Tip

• Focus on definitions: Always define terms like microprocessor, von Neumann architecture, memory hierarchy, and SAP-1.
• Draw diagrams: Expect block diagrams of SAP-1, memory hierarchy, and instruction formats in exams.
• Trace execution: For questions like "Explain the fetch-decode-execute cycle of LDA", show step-by-step register changes and timing.
• Compare RISC/CISC: Use a table to highlight differences and give real-world examples (e.g., ARM in smartphones vs. x86 in PCs).
• Memory hierarchy: Know the trade-offs (speed vs. cost) and where each level is used (e.g., registers for CPU operations, disk for long-term storage).
• SAP-1 vs. SAP-2: If asked, mention that SAP-2 introduces multi-address instructions (e.g., ADD R1, R2, R3), while SAP-1 is single-address.