IT233 Digital Logic

Digital LogicUnit 513 min read

Sequential Circuits & State Machines: Design, Analysis & Applications

Unit 5 of Digital Logic covers sequential circuits (flip-flops, registers, counters) and state machines (FSMs), explaining their design procedures, state diagrams, excitation tables, and real-world applications in digital systems like traffic lights, eSewa payment flows, and Pathao ride allocation.

TAKEAWAYS:

  • Sequential circuits remember past inputs (unlike combinational circuits) using feedback loops and storage elements like flip-flops.
  • A state machine is a sequential circuit modeled as states (conditions) and transitions (actions) triggered by inputs.
  • Design steps for state machines: state diagram → state table → excitation table → flip-flop circuit → output logic.
  • Moore vs. Mealy machines: Moore outputs depend only on the current state; Mealy outputs depend on both state and inputs.
  • Real-world examples: eSewa’s payment verification (FSM), Daraz’s order queue (shift registers), and NTC’s traffic signal control (counters).
  • Exam focus: Always draw state diagrams, excitation tables, and circuit diagrams for full marks.

1. Sequential vs. Combinational Circuits: Key Differences

Sequential circuits store information (memory) and their outputs depend on both current and past inputs, while combinational circuits depend only on current inputs. The key difference lies in feedback loops (memory elements like flip-flops).

CombinationalOutput depends only on current inputsNo memorySequentialOutput depends on current + past inputsHas memory (flip-flops)
Key difference: Sequential circuits use feedback loops for memory.

Why it matters:

  • Combinational: Used for instant calculations (e.g., ALU in a CPU).
  • Sequential: Used for timing-dependent operations (e.g., clock synchronization in eSewa transactions).

2. Flip-Flops and Latches: The Building Blocks of Memory

Flip-flops and latches are binary storage elements that hold a bit (0 or 1) until changed by an input signal. They are the foundation of sequential circuits.

Types of Flip-Flops

Type Symbol Triggering Edge Output Change Timing Use Case
SR Latch ![SR Latch](IMAGE: SR latch circuit diagram) Level-sensitive Immediate (asynchronous) Basic memory storage
D Flip-Flop ![D Flip-Flop](IMAGE: D flip-flop symbol) Clock edge On clock edge (synchronous) Registers, state machines
JK Flip-Flop ![JK Flip-Flop](IMAGE: JK flip-flop symbol) Clock edge On clock edge Counters, sequential logic
T Flip-Flop ![T Flip-Flop](IMAGE: T flip-flop symbol) Clock edge On clock edge Toggle applications (e.g., counters)

Key Properties:

  • SR Latch: Has an indeterminate state if S=1 and R=1 (both inputs high). To avoid this, use JK or D flip-flops.
  • Clocked Flip-Flops: Change state only on a clock edge (synchronous operation), making them reliable in digital systems.

Example: SR Latch with Indeterminate State

SR
SR Latch with indeterminate state (S=1, R=1) highlighted.

Problem: If S=1 and R=1, the output is undefined (both Q and Q’ may go high temporarily). Solution: Use JK flip-flop (where J=1 and K=1 toggles the output safely).


3. Sequential Circuit Design: Step-by-Step

Designing a sequential circuit involves modeling behavior as states and then implementing it with flip-flops.

Step 1: Define the State Diagram

A state diagram represents the conditions (states) and transitions of a sequential circuit. Example: A traffic light controller (red → green → yellow → repeat).

stateDiagram-v2
    [*] --> Red
    Red --> Green : [Timer Expires]
    Green --> Yellow : [Timer Expires]
    Yellow --> Red : [Timer Expires]
    Red --> [*]

Step 2: Convert State Diagram to State Table

List all states, inputs, and next states.

Present State Input (Button Press) Next State Output (Light)
Red 0 (No press) Green Red ON
Green 0 (No press) Yellow Green ON
Yellow 0 (No press) Red Yellow ON

Step 3: Derive Excitation Table

Determine the flip-flop inputs (J, K, T, D) needed to transition between states.

Present State Next State J K T Output
Red (00) Green (01) 1 - - Red ON
Green (01) Yellow (10) - 1 - Green ON
Yellow (10) Red (00) 1 1 - Yellow ON

Step 4: Implement with Flip-Flops

Use JK flip-flops (since they handle toggling well) and design the circuit.

Step 5: Add Output Logic

Use combinational logic (AND/OR gates) to generate outputs from states.

Example: For the traffic light, use a decoder to light up the correct bulb.

Red LightGreen LightYellow LightState Bit 1State Bit 2
Decoder logic for traffic light outputs (simplified).

4. Finite State Machines (FSMs)

An FSM is a mathematical model of a sequential circuit with:

  • States (conditions the system can be in).
  • Inputs (trigger transitions).
  • Outputs (actions based on state/input).
startabaq0q1q2
Example DFA: Simple pattern recognition (01*0).

Types of FSMs

Type Output Depends On Example
Moore Only current state Traffic light (output changes only at state change)
Mealy State + Input eSewa payment verification (output depends on current input)

Example: Moore Machine (Traffic Light)

startTimerTimerTimerRedGreenYellow
Moore Machine: Traffic Light Controller (outputs depend only on state).

Example: Mealy Machine (eSewa Payment Flow)

startUser Enters PINPIN CorrectPIN WrongWaitingForPaymentVerifyingApprovedRejected
Mealy Machine: eSewa Payment Flow (outputs depend on state + input).

5. Designing a Sequential Circuit: Worked Example

Problem: Design a 3-bit binary up-counter using JK flip-flops.

Step 1: State Diagram

A 3-bit counter cycles through 000 → 001 → 010 → ... → 111 → 000.

stateDiagram-v2
    [*] --> 000
    000 --> 001 : [Clock]
    001 --> 010 : [Clock]
    010 --> 011 : [Clock]
    011 --> 100 : [Clock]
    100 --> 101 : [Clock]
    101 --> 110 : [Clock]
    110 --> 111 : [Clock]
    111 --> 000 : [Clock]

Step 2: Excitation Table

For each bit, determine when it toggles (T=1).

Present State Next State JK Flip-Flop 1 (LSB) JK Flip-Flop 2 JK Flip-Flop 3 (MSB)
000 001 T=1 (toggle) T=0 T=0
001 010 T=1 T=0 T=0
010 011 T=1 T=0 T=0
011 100 T=1 T=1 T=0
... ... ... ... ...

Step 3: Circuit Implementation

Use JK flip-flops with T input tied to J=K=1 (toggle mode).

Real-World Tie-In:

  • Pathao’s ride allocation uses a counter-based FSM to assign drivers to requests in sequence.
  • NTC traffic signals use 3-bit counters to cycle through red, green, and yellow.

6. Shift Registers: Serial-to-Parallel Conversion

A shift register stores bits and shifts them on each clock pulse. Used in data transmission, memory, and serial communication.

Types of Shift Registers

Type Operation Example Use Case
Serial-In/Serial-Out (SISO) Shifts bits in and out serially Simple data delay line
Serial-In/Parallel-Out (SIPO) Shifts in serially, outputs parallel ADC data capture
Parallel-In/Serial-Out (PISO) Loads parallel, shifts out serially Printer data transmission
Parallel-In/Parallel-Out (PIPO) Loads and outputs in parallel Memory registers

Example: 3-bit SIPO Shift Register

Real-World Example:

  • Khalti’s transaction logs use shift registers to temporarily store pending transactions before processing.
  • Daraz’s order queue processes orders in FIFO (First-In-First-Out) order using shift registers.

7. Practical Applications of Sequential Circuits

Application Sequential Circuit Used How It Works
Traffic Light Controller Counter + FSM Cycles through states using a 3-bit counter.
eSewa Payment Verification Mealy Machine Checks PIN input and approves/rejects payment.
Pathao Ride Allocation Priority Encoder + FSM Assigns nearest driver using a state machine.
NTC Call Routing Shift Register Stores call numbers in a queue.
Bank Loan Interest Calculation Counter + ALU Tracks loan periods using a counter.

In the Real World

  1. eSewa’s Payment Flow (Mealy Machine)

    • How it uses FSMs: When you enter your PIN, eSewa’s server acts as a Mealy machine:
      • State 1: Waiting for PIN.
      • State 2: Verifying PIN (output depends on whether PIN is correct).
      • State 3: Approving/Rejecting transaction.
    • Key Idea: The output (approval/rejection) depends on both the current state (PIN entered) and the input (PIN correctness).
  2. Daraz’s Order Queue (Shift Register + FSM)

    • How it uses sequential circuits:
      • Orders are stored in a FIFO queue (implemented with shift registers).
      • A state machine processes each order (e.g., "Order Received" → "Processing" → "Shipped").
    • Key Idea: The shift register ensures orders are processed in the correct sequence, while the FSM handles each order’s status.
  3. NTC Traffic Signals (Counter + Decoder)

    • How it uses sequential circuits:
      • A 3-bit counter cycles through 000 (Red) → 001 (Green) → 010 (Yellow) → 000.
      • A decoder lights up the correct bulb based on the counter’s output.
    • Key Idea: The counter’s state determines which light is ON, making it a Moore machine.

Exam Tip

  1. Always draw the state diagram first – Examiners check if you understand the problem.
  2. Use excitation tables – Partial marks are given for correct J/K/T/D inputs.
  3. Label your circuit clearly – Show clock, inputs, outputs, and flip-flop types.
  4. For counters/registers, show the bit-wise operation (e.g., how LSB toggles every clock).
  5. Moore vs. Mealy: If the question asks for output logic, specify whether it’s state-dependent (Moore) or input-dependent (Mealy).
  6. Real-world tie-ins: If asked for an application, mention eSewa (FSM), Daraz (shift registers), or NTC (counters).

Based on the TU BITM syllabus for Digital Logic (IT233), unit 5.

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