PLDs, Encoders/Decoders: Design, Truth Tables & Real-World Logic

TAKEAWAYS:

• Understand PLDs (PROM, PLA, PAL, FPGA) as reprogrammable logic chips that replace fixed circuits, reducing hardware costs and design time.
• Decoders convert binary inputs to unique active outputs (e.g., memory addressing), while encoders do the reverse (e.g., priority interrupt systems).
• Don’t-care conditions in encoders (e.g., unused input combinations) simplify logic design by allowing flexible output assignments.
• JK flip-flops (used in PLDs) eliminate the race-around problem of SR flip-flops, enabling stable sequential operations.
• Real-world applications include eSewa’s payment routing (decoders for transaction types) and Ncell’s call priority (encoders for emergency lines).
• Master design techniques: cascading decoders (e.g., 4×16 from 2×4), minimizing don’t-cares, and using PLDs for prototyping.

1. Programmable Logic Devices (PLDs): The Reprogrammable Logic Backbone

PLDs are customizable integrated circuits that replace fixed logic gates, decoders, or multiplexers. They eliminate the need for discrete components, reducing cost, power, and board space. The syllabus focuses on four types:

Types of PLDs

Key Idea:

• PROM (Programmable Read-Only Memory): AND gates fixed; OR gates programmable (e.g., used in early firmware storage).
• PLA (Programmable Logic Array): Both AND/OR arrays programmable → more flexible but slower.
• PAL (Programmable Array Logic): AND array programmable; OR array fixed → faster, used in control units.
• FPGA (Field-Programmable Gate Array): Modern PLD with configurable logic blocks (CLBs) and interconnects, reprogrammable via software (e.g., Xilinx, Altera).

Real-World Example:

2. Decoders: Binary-to-Line Converters

Decoders take n inputs and activate one of $2^n$ outputs uniquely. They are the backbone of memory addressing, 7-segment displays, and demultiplexers.

How a Decoder Works

A 3×8 decoder (e.g., 74LS138) has:

• 3 inputs (A, B, C) → $2^3=8$ outputs (Y0 to Y7).
• Enable inputs (G1, G2, G2̅) to activate the decoder.
• Truth Table:

  A	B	C	Y0	Y1	Y2	Y3	Y4	Y5	Y6	Y7
  0	0	0	1	0	0	0	0	0	0	0
  0	0	1	0	1	0	0	0	0	0	0
  ...	...	...	...	...	...	...	...	...	...	...

Logic Diagram:

Worked Example: Design a 4×16 Decoder Using 2×4 Decoders Problem: Use two 2×4 decoders (e.g., 74LS139) to build a 4×16 decoder. Solution:

1. Inputs: A, B, C, D (4 bits → 16 outputs).
2. Split inputs:
   • Use A, B to select between the two 2×4 decoders (via their enable inputs).
   • Use C, D as inputs to the selected decoder.
3. Circuit:

• When B=0, Decoder 1 is enabled (outputs Y0–Y7).
• When B=1, Decoder 2 is enabled (outputs Y8–Y15).

Real-World Tie-In: In eSewa’s payment gateway, a 4×16 decoder routes transactions to 16 different bank servers based on a 4-bit transaction code (e.g., 0000 = Nabil Bank, 0001 = Global IME).

3. Encoders: Line-to-Binary Converters

Encoders do the reverse of decoders: they convert active high/low inputs into a binary code. They are used in:

• Priority interrupt systems (e.g., CPU handling multiple requests).
• Keyboard scanners (e.g., detecting which key is pressed).
• Analog-to-digital converters (ADC).

8×3 Encoder Design

An 8×3 encoder has:

• 8 inputs (I0 to I7).
• 3 outputs (A, B, C).
• Don’t-care conditions: Only one input is active at a time (e.g., keyboard keys).

Truth Table (with don’t-cares):

Key Insight:

• Don’t-cares (X) can be used to simplify the logic (e.g., assign A=0 for unused inputs to reduce gates).
• Number of don’t-cares: For an 8×3 encoder, $2^8-8=248$ combinations are unused (but only the 7 unused input combinations matter for simplification).

Logic Diagram:

flowchart LR
    I0["I0"] --> OR1["OR Gate"]
    I1["I1"] --> OR2["OR Gate"]
    OR1 --> A["A=0"]
    OR2 --> A
    I2 --> OR3["OR Gate"]
    OR3 --> B["B=0"]
    I4 --> OR4["OR Gate"]
    OR4 --> B
    I1 --> OR5["OR Gate"]
    OR5 --> C["C=0"]
    I2 --> OR6["OR Gate"]
    OR6 --> C
    I4 --> OR7["OR Gate"]
    OR7 --> C

Worked Example: Simplify an 8×3 Encoder Using Don’t-Cares Problem: Design the output A for an 8×3 encoder, minimizing gates. Solution:

1. From the truth table, A=1 only when I4, I5, I6, or I7 are active.
2. Use don’t-cares to simplify:
   • Assign A=0 for unused inputs (e.g., I8 to I15 if extended).
3. Simplified expression: $A=I4+I5+I6+I7$ (No further simplification needed.)

Real-World Example:

4. JK Flip-Flop vs. SR Flip-Flop: Why JK Wins

Both are sequential circuits, but JK flip-flops solve the race-around problem of SR flip-flops.

Comparison Table

JK Flip-Flop Truth Table:

Logic Diagram:

Why JK is Better:

• No forbidden state: J=K=1 toggles the output (useful for counters).
• Stable operation: No risk of undefined behavior during clock transitions.

Real-World Use: In Khalti’s transaction logging, JK flip-flops in the PLD track the state of each transaction (e.g., pending → completed) without race conditions.

5. Practical Design: Encoder + Decoder = Priority Interrupt System

Problem: Design a system where 8 devices (I0–I7) send interrupt requests to a CPU. The CPU must service the highest-priority request (I0 > I1 > ... > I7).

Solution:

1. Encoder: Convert the active interrupt line to a 3-bit code.
2. Priority Logic: Use don’t-cares to ensure only the highest-priority active input is encoded.
3. Decoder: Use the encoded output to select the device.

Circuit:

flowchart LR
    I0["I0"] --> EN["Encoder"]
    I1["I1"] --> EN
    ...
    I7["I7"] --> EN
    EN --> A["A"]
    EN --> B["B"]
    EN --> C["C"]
    A --> DE["Decoder"]
    B --> DE
    C --> DE
    DE --> CPU["CPU"]

Truth Table for Priority Encoder:

Key Trick:

• Assign don’t-cares to prevent lower-priority inputs from overriding higher ones. For example, if I1 and I0 are both active, the encoder must output 000 (I0’s code).

Exam Tip

1. Memorize Standard ICs:

   • 74LS138: 3×8 decoder.
   • 74LS148: 8×3 priority encoder.
   • 74LS112: JK flip-flop (master-slave).

2. Don’t-Care Conditions:

   • Always list unused input combinations in encoders (e.g., "7 don’t-cares in 8×3 encoder").
   • Use them to simplify logic (e.g., assign 0 to unused inputs to reduce gates).

3. Design Steps for PLDs/Encoders/Decoders:

   • Step 1: Draw the truth table.
   • Step 2: Identify don’t-cares.
   • Step 3: Simplify using Boolean algebra or K-maps.
   • Step 4: Draw the circuit (use standard ICs if possible).

4. Common Pitfalls:

   • Forgetting enable inputs in decoders (e.g., 74LS138 has G1, G2, G2̅).
   • Ignoring priority in encoders (e.g., I0 must override I1).
   • Misusing JK flip-flops (e.g., forgetting the toggle mode on J=K=1).

5. Real-World Questions:

   • Expect applications (e.g., "How is a decoder used in eSewa?").
   • Trace signals: For example, "Show how a 4×16 decoder routes a 4-bit input to one of 16 outputs."

Final Note: PLDs and encoders/decoders are the building blocks of digital systems. Master their truth tables, don’t-care conditions, and design techniques—this is how you’ll score full marks in both theoretical and practical questions. For the exam, practice designing cascaded decoders and priority encoders from scratch.