Interrupts & DMA: Handling Events & Data Transfers

TAKEAWAYS:

• Interrupts allow the CPU to respond to asynchronous events (e.g., keyboard input, timer overflow) via maskable (software-controllable) or non-maskable (critical) types.
• Priority interrupts (daisy-chain, polling, vectored) determine which event the CPU handles first, balancing urgency and fairness.
• DMA bypasses the CPU for bulk data transfers (e.g., disk reads, network packets) using dedicated DMA channels and handshake signals (HOLD, HLDA, DREQ, DACK).
• 8085-specific pins: TRAP (non-maskable), INTR (maskable), RST 7.5/6.5 (vectored), and DMA pins (HOLD, HLDA, DREQ0-7, DACK0-7).
• Trade-offs: Interrupts reduce CPU overhead but add latency; DMA speeds up I/O but increases hardware complexity.
• Real-world ties: WhatsApp uses interrupts for message notifications; Daraz’s order queue relies on DMA-like bulk data transfers to databases.

1. Interrupts: The CPU’s Event-Handling System

1.1 What is an Interrupt?

An interrupt is a signal sent to the CPU by hardware or software to request immediate attention. Unlike polling (where the CPU repeatedly checks for events), interrupts enable asynchronous processing, improving efficiency.

Why use interrupts?

• Efficiency: The CPU doesn’t waste cycles waiting for I/O (e.g., keyboard input, timer ticks).
• Prioritization: Critical events (e.g., power failure) can preempt less urgent tasks.
• Modularity: Peripherals (e.g., printers, sensors) can notify the CPU only when needed.

1.2 Types of Interrupts

*Maskable interrupts can be disabled via the interrupt mask bit (e.g., EI/DI in 8085).

1.3 How Interrupts Work: The Interrupt Cycle

sequenceDiagram
    participant CPU
    participant Peripheral
    participant ISR

    Peripheral->>CPU: Sends interrupt signal (e.g., INTR)
    CPU-->>Peripheral: Acknowledges (INTA)
    Peripheral->>CPU: Sends interrupt vector (type)
    CPU->>CPU: Saves PC, flags to stack
    CPU->>ISR: Jumps to ISR (Interrupt Service Routine)
    ISR->>CPU: Executes handler (e.g., read keyboard)
    ISR->>CPU: Restores PC, flags
    CPU-->>Peripheral: Sends EOI (End of Interrupt)

Key Steps:

1. Interrupt Request: Peripheral asserts INTR (maskable) or TRAP (non-maskable).
2. Acknowledgment: CPU sends INTA (Interrupt Acknowledge) and reads the interrupt vector (type).
3. Context Switch: CPU pushes PC, PSW (Program Status Word) to stack and jumps to the ISR.
4. Service: ISR executes (e.g., reads data, updates registers).
5. Return: IRET instruction restores the old context; CPU resumes normal execution.

1.4 Priority Interrupt Schemes

When multiple interrupts occur simultaneously, the CPU must decide which to handle first. Three common methods:

A. Daisy-Chain Priority

• Peripherals are daisy-chained (connected in series).
• The CPU sends INTA; the highest-priority peripheral (closest to CPU) responds first.
• If it doesn’t respond, the signal propagates to the next device.

graph LR
    CPU["CPU"] -->|"INTA"| P1["Printer (Highest Priority)"]
    P1 --> P2["Keyboard"]
    P2 --> P3["Disk"]

Pros: Simple wiring. Cons: Slow if low-priority devices are checked first.

B. Polling Priority

• CPU checks devices in a fixed order (e.g., timer → keyboard → disk).
• Used in systems with few peripherals (e.g., 8085).

Example (8085):

    IN 0x80    ; Check timer
    JNZ HANDLE_TIMER
    IN 0x81    ; Check keyboard
    JNZ HANDLE_KEYBOARD
    ...

C. Vectored Interrupt

• Each interrupt has a unique vector (address) stored in a vector table.
• CPU jumps directly to the ISR without polling.
• Used in modern systems (e.g., x86 INT n).

Example (8085 Vectored Interrupts):

1.5 Real-World Example: WhatsApp Notifications

• Interrupt Type: Hardware (mobile’s timer interrupt or network stack interrupt).
• How It Works:
  1. When a message arrives, the network chip (e.g., Qualcomm modem) triggers an interrupt.
  2. The CPU’s ISR reads the message from RAM and updates the WhatsApp app’s notification counter.
  3. The display driver (another interrupt) updates the screen.
• Why Not Polling? Polling would waste battery life checking for messages every millisecond. Interrupts wake the CPU only when needed.

2. Direct Memory Access (DMA): Bypassing the CPU

2.1 What is DMA?

DMA allows peripherals to transfer data directly to/from memory without CPU intervention. Used for high-speed I/O (e.g., disk reads, network packets).

Why DMA?

• Speed: CPU isn’t bottlenecked by slow I/O (e.g., reading a 1GB file).
• Efficiency: CPU can execute other tasks while DMA transfers data.

2.2 How DMA Works

sequenceDiagram
    participant CPU
    participant DMA_Controller
    participant Peripheral
    participant Memory

    Peripheral->>DMA_Controller: Requests transfer (DREQ)
    DMA_Controller->>CPU: Sends HOLD (CPU pauses)
    CPU-->>DMA_Controller: Acknowledges HLDA
    DMA_Controller->>Memory: Reads/Writes data (via bus)
    DMA_Controller->>CPU: Releases HOLD
    CPU->>CPU: Resumes execution

Key Components:

1. DMA Controller: Manages transfers (e.g., sets source/destination addresses, count).
2. DMA Channel: A dedicated path for data (e.g., DREQ0 for disk, DREQ1 for network).
3. Handshake Signals:
   • DREQ (Data Request): Peripheral signals it’s ready.
   • DACK (Data Acknowledge): DMA controller grants access.
   • HOLD/HLDA: CPU temporarily yields the bus.

2.3 DMA Modes

2.4 DMA in 8085 Microprocessor

The 8085 lacks a built-in DMA controller, but external chips (e.g., Intel 8257) handle DMA via these pins:

Example (8085 DMA Transfer):

1. Disk controller asserts DREQ0.
2. CPU checks DREQ0 and, if enabled, asserts HLDA and releases the bus.
3. DMA controller transfers data directly to memory via the data bus.
4. After transfer, DMA controller deasserts HLDA, and CPU resumes.

2.5 Real-World Example: Daraz Order Processing

• DMA Use Case: When you place an order on Daraz, the database server (e.g., PostgreSQL) uses DMA to:
  1. Read product details from SSD storage (DMA transfers data blocks to RAM).
  2. Write order confirmation to logs (DMA writes to disk without CPU stalls).
• Why DMA?
  • Without DMA, the CPU would spend 90% of its time moving data between RAM and disk.
  • DMA allows the CPU to handle thousands of orders per second while background processes run.

3. Interrupts vs. DMA: Key Differences

4. Exam-Focused Worked Example

Problem:

In an 8085 system, a peripheral sends an interrupt via the INTR pin. The ISR for this interrupt is located at 0x003C. Show the steps the CPU takes to service this interrupt, including stack operations.

Solution:

1. Interrupt Request:

   • Peripheral asserts INTR (maskable).
   • CPU checks EI flag (if enabled) and INTR pin.

2. Acknowledge and Vector Fetch:

   • CPU sends INTA and reads the interrupt vector (RST 7.5).
   • RST 7.5 corresponds to address 0x003C.

3. Context Save:

   • CPU pushes PC (Program Counter) and PSW (Program Status Word) to the stack.
   • Stack pointer (SP) decrements by 2 for each byte.

4. Jump to ISR:

   • CPU loads PC with 0x003C and executes the ISR.

5. ISR Execution:

   • Example ISR (pseudo-assembly):

     ORG 0x003C
     ISR:
         PUSH B    ; Save registers
         PUSH D
         ; Handle interrupt (e.g., read data)
         IN 0x80   ; Read from peripheral
         POP D     ; Restore registers
         POP B
         EI        ; Re-enable interrupts
         RET       ; Return from interrupt
     

6. Return:

   • RET instruction pops PSW and PC from the stack.
   • CPU resumes execution after the interrupted instruction.

5. Common Pitfalls and Exam Tips

A. Interrupts

• Maskable vs. Non-Maskable:

  • Always distinguish between INTR (maskable) and TRAP (non-maskable).
  • Example question: "Why can’t a program disable a TRAP interrupt?" → Answer: It’s hardware-critical (e.g., memory errors).

• Priority Schemes:

  • Know the daisy-chain (8085) vs. vectored (modern) methods.
  • Example: "In daisy-chain, how does the CPU know which device triggered the interrupt?" → Answer: The first responding device sends its vector.

• Stack Operations:

  • Interrupts always save PC and PSW to the stack. Forgetting this in an exam answer = 0 marks.

B. DMA

• Pins Matter:

  • For 8085, memorize:
    • HOLD/HLDA (bus request/acknowledge).
    • DREQ/DACK (data request/acknowledge).
  • Example question: "Name the pin used for DMA in 8085." → Answer: HOLD (or DREQ0-7 for channels).

• DMA vs. Interrupts:

  • DMA is for bulk data; interrupts are for events.
  • Example: "Why use DMA to read a file instead of interrupts?" → Answer: Interrupts would require CPU involvement for every byte.

• Performance Trade-off:

  • DMA speeds up I/O but adds hardware cost (DMA controller).
  • Example: "When would you avoid DMA?" → Answer: In low-cost systems (e.g., embedded devices) where a DMA chip isn’t feasible.

6. Real-World Applications in Nepal

A. eSewa Payments

• Interrupts: When you scan a QR code, the NFC chip in your phone triggers an interrupt to wake the CPU and process the payment.
• DMA: The secure element (dedicated chip for payments) uses DMA to transfer transaction data to the bank’s server without exposing it to the main CPU.

B. NTC’s Traffic Management System

• Interrupts: Traffic lights at busy intersections (e.g., Thapathali) use timer interrupts to switch signals every 30 seconds.
• DMA: CCTV cameras stream video to servers using DMA to avoid CPU bottlenecks.

C. NEPSE Stock Trading

• DMA: When you buy/sell shares, the trading server uses DMA to log transactions to disk faster than the CPU could handle via interrupts.

Exam Tip

1. For Interrupts:

   • Always draw the interrupt cycle (sequence diagram) if asked about flow.
   • Compare daisy-chain vs. polling vs. vectored in a table.
   • Memorize 8085 interrupt vectors (RST 7.5, TRAP).

2. For DMA:

   • Sketch the DMA handshake (HOLD/HLDA, DREQ/DACK).
   • Relate DMA to real systems (e.g., "How does Daraz use DMA?").
   • Know the pins for 8085 DMA (HOLD, DREQ0-7).

3. Worked Examples:

   • If given an 8085 interrupt scenario, show stack operations (push/pop PC, PSW).
   • For DMA, describe the bus cycle (CPU pauses, DMA takes over).

stateDiagram-v2
    [*] --> Idle
    Idle --> InterruptRequest : Peripheral triggers INTR
    InterruptRequest --> Acknowledge : CPU sends INTA
    Acknowledge --> SaveContext : Push PC, PSW to stack
    SaveContext --> ExecuteISR : Jump to ISR
    ExecuteISR --> RestoreContext : POP PC, PSW
    RestoreContext --> [*]