Microprocessor Architecture: Internal Blocks, Bus Structure & Functional Units

TAKEAWAYS:

• The 8085 microprocessor has 5 major functional blocks: Arithmetic Logic Unit (ALU), Control Unit (CU), Register Array, Timing and Control Unit, and Instruction Register.
• The bus structure (address, data, control) connects the CPU to memory and I/O devices, with 8085 using 8-bit data bus and 16-bit address bus for 64KB addressable memory.
• Registers (A, B, C, D, H, L, SP, PC, PSW) store operands, addresses, and flags, with PC (Program Counter) holding the next instruction address.
• Interrupts (TRAP, RST 7.5, RST 6.5, RST 5.5) allow external devices to pause CPU execution, while DMA (Direct Memory Access) pins (HOLD, HLDA) enable high-speed data transfer without CPU intervention.
• Performance depends on clock speed (8085: 3 MHz), instruction cycle time (4 clock cycles per machine cycle), and pipelining (not in 8085 but in modern CPUs).
• Real-world ties: Banks use DMA for high-speed transaction processing (e.g., Nabil Bank’s ATM networks), while mobile apps (Pathao, eSewa) rely on CPU’s interrupt-driven I/O for real-time updates.

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1. Introduction to Microprocessor Architecture

A microprocessor is the central processing unit (CPU) of a computer system, integrating arithmetic, logic, control, and memory management functions on a single chip. The 8085 microprocessor (an 8-bit CPU) is a classic example studied in this unit. Its architecture defines how it fetches, decodes, and executes instructions, interacts with memory/I/O, and handles interrupts.

Why Study 8085?

• Foundation for modern CPUs: Concepts like bus structures, registers, and pipelining apply to today’s processors (Intel Core i7, ARM Cortex).
• Exam focus: TU/PU exams often ask for block diagrams, pin descriptions, and timing diagrams of 8085.
• Real-world relevance: Used in embedded systems (microwaves, washing machines) and legacy systems (industrial controllers).

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2. Functional Blocks of 8085 Microprocessor

The 8085’s architecture is divided into 5 key blocks, each with a specific role. Below is its internal organization with a Mermaid block diagram for clarity.

Key Components Explained

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3. Registers in 8085: Storage and Control

Registers are small, high-speed memory locations inside the CPU. The 8085 has 8 general-purpose registers, 2 special registers, and 1 flag register.

Types of Registers

Special Registers

• Stack Pointer (SP): Used for subroutine calls and interrupts.
  • Example: When CALL 2000H is executed, PC is pushed onto the stack, and SP decrements by 2.
• Program Counter (PC): Always points to the next instruction.
  • Example: After JMP 3000H, PC = 3000H.

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WORKED EXAMPLE: Register Usage in a Loop Consider this assembly code snippet (for 8085):

MVI B, 5      ; Load B with 5
LOOP:         ; Label
DCR B         ; Decrement B
JNZ LOOP      ; Jump if B ≠ 0

Trace the registers:

1. MVI B, 5 → B = 5, PC = next instruction.
2. DCR B → B = 4, Zero flag = 0 (since B ≠ 0).
3. JNZ LOOP → PC jumps back to LOOP (since Zero flag = 0).
4. Repeat until B = 0 → loop exits.

Real-world tie: This is how Pathao’s ride-allocation algorithm checks if a driver is available (loop until a driver accepts the request).

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4. Bus Structure: Connecting CPU to Memory/I/O

The bus system acts as a communication highway between the CPU, memory, and I/O devices. The 8085 has three buses:

Bus Timing Diagram

The 8085 uses 4 clock cycles (T1-T4) per machine cycle (e.g., memory read/write). Below is a simplified timing diagram for a memory read cycle:

Key Signals:

• ALE (Address Latch Enable): Latches the lower 8 bits of the address (since address bus is multiplexed).
• MREQ (Memory Request): Asserted when CPU accesses memory.
• RD (Read): Pulls data from memory to CPU.

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5. Interrupts and DMA: Handling External Events

Interrupts in 8085

Interrupts allow external devices to pause CPU execution and request service. The 8085 supports:

• Maskable Interrupts: Can be disabled by setting the interrupt enable (IE) flag.
• Non-Maskable Interrupt (TRAP): Cannot be disabled (used for critical errors).

How Interrupts Work:

1. Device asserts INTR pin.
2. CPU finishes current instruction → checks IE flag.
3. If enabled, CPU executes RST n (jumps to vector address).
4. CPU executes Interrupt Service Routine (ISR) → clears interrupt → resumes normal execution.

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WORKED EXAMPLE: Interrupt-Driven Keyboard Input Suppose a keyboard sends an interrupt via RST 7.5 (vector 3CH).

1. User presses a key → keyboard sends INTR signal.
2. CPU jumps to 3CH (ISR location).
3. ISR reads the key from the keyboard buffer.
4. CPU returns from interrupt → continues execution.

Real-world tie: eSewa’s OTP system uses interrupts to detect when a user enters their PIN (via RST 7.5).

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Direct Memory Access (DMA)

DMA allows high-speed I/O devices (e.g., hard drives, network cards) to transfer data directly to/from memory without CPU intervention.

DMA Pins in 8085:

• HOLD: Requests DMA access.
• HLDA (Hold Acknowledge): CPU releases buses.

DMA Transfer Steps:

1. Device asserts HOLD.
2. CPU asserts HLDA → releases buses.
3. Device transfers data directly to memory.
4. CPU resumes after DMA completes.

Real-world tie: Nabil Bank’s ATM network uses DMA to transfer transaction data to/from the central server without CPU delays.

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6. Performance Considerations

The 8085’s performance depends on:

1. Clock Speed: 3 MHz (slower than modern CPUs but sufficient for embedded systems).
2. Instruction Cycle Time: 4 clock cycles per machine cycle (e.g., MOV A,B takes 4 cycles).
3. Pipelining: Not used in 8085 (unlike modern CPUs like Intel Core i7).

Comparison: 8085 vs. Modern CPUs

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7. Real-World Applications

Example 1: Banking Systems (Nabil Bank, Global IME)

• Concept Used: Interrupts + DMA
• How?
  • Interrupts: ATMs use RST 7.5 to signal when a card is inserted.
  • DMA: High-speed transaction data (e.g., card swipes) are transferred directly to memory without CPU delays.

Example 2: Mobile Apps (Pathao, eSewa)

• Concept Used: Registers + Control Unit
• How?
  • Pathao’s ride allocation: Uses the PC (Program Counter) to jump between driver availability checks (loop until a driver accepts).
  • eSewa’s OTP verification: Uses interrupts to detect key presses during OTP entry.

Example 3: E-Commerce (Daraz, Amazon)

• Concept Used: Bus Structure + Memory Organization
• How?
  • Order processing: When you click "Buy Now," the CPU uses the address bus to fetch product details from memory and the data bus to send payment info to the server.
  • Inventory updates: DMA transfers bulk data (e.g., 1000 orders) directly to memory for faster processing.

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8. Exam Tips

1. Block Diagrams: Always draw the 8085 internal architecture with all 5 blocks (ALU, CU, registers, etc.) in exams.
2. Bus Structure: Memorize the widths (16-bit address bus, 8-bit data bus) and key signals (ALE, MREQ, RD).
3. Registers: Know the size and function of each register (e.g., SP is 16-bit, PC holds the next instruction address).
4. Interrupts: Differentiate between maskable (RST 5.5, 6.5, 7.5) and non-maskable (TRAP) interrupts.
5. DMA: Remember the HOLD/HLDA pins and when DMA is used (high-speed I/O).
6. Worked Examples: Practice register traces (e.g., how PC changes in loops/jumps) and bus timing diagrams.
7. Real-world ties: Link concepts to banks (DMA), apps (interrupts), and e-commerce (bus structure) in explanations.

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Final Note: This unit is heavily diagram-based in exams. Practice drawing:

• Internal block diagram of 8085.
• Bus timing diagrams (memory read/write).
• Register transfer traces (e.g., MOV, JMP, CALL instructions).

Good luck! 🚀