Addressing Modes & Instruction Set: How CPUs Access Data & Execute Code

TAKEAWAYS:

• Addressing modes determine how operands are specified (e.g., immediate, register, memory), directly impacting instruction efficiency and code size.
• Instruction sets define the CPU’s native commands (data transfer, arithmetic, logic, control), categorized by function and operands.
• 8085 vs. 8086 differ in addressing modes (e.g., 8086’s segment:offset vs. 8085’s direct/indirect) and instruction formats (1-byte vs. multi-byte).
• Worked examples show how addressing modes resolve operands (e.g., MVI A, 50H vs. LDA 2050H) and how pipelines execute instructions in stages.
• Real-world ties: eSewa’s transaction queues use indirect addressing for dynamic data access; Daraz’s order processing relies on stack-based control instructions.
• Exam focus: Define modes/instructions precisely, trace operand resolution, and compare architectures (e.g., "Why does 8086 use segment registers?").

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1. Addressing Modes: How the CPU Finds Operands

Addressing modes specify how an instruction’s operand is located. The 8085 microprocessor supports 6 modes, while the 8086 adds segmented addressing. Below is a comparison table and visual breakdown.

1.1 Classification of Addressing Modes

1.2 Key Modes in 8085 vs. 8086

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1.3 Worked Example: Operand Resolution

Problem: Trace how the instruction LDA 2050H works in 8085.

1. Instruction Format:

   Opcode: 3A (LDA)
   Address: 2050H (16-bit)
   

2. Steps:
   • CPU decodes 3A as LDA (load accumulator from memory).
   • Address bus outputs 2050H.
   • Memory reads data at 2050H and sends it to the accumulator (A).
3. Real-World Tie:
   • eSewa’s transaction processing: When you pay a bill, eSewa uses direct addressing to fetch your account balance from a fixed memory location (e.g., STA 5000H stores your balance). If dynamic data (e.g., recent transactions) is accessed, indirect addressing (e.g., LHLD with a pointer register) is used.

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2. Instruction Set: The CPU’s Command Language

The instruction set defines the native commands a microprocessor understands. Instructions are classified into 5 categories:

2.1 Data Transfer Instructions

Definition: Move data between registers, memory, and I/O ports. Examples:

• 8085:
  • MOV B, C (register to register)
  • LDA 2050H (memory to accumulator)
  • STA 3000H (accumulator to memory)
• 8086:
  • MOV AX, BX (register to register)
  • MOV [SI], AL (register to memory via SI)

Worked Example: Problem: Write instructions to swap the contents of registers B and C in 8085. Solution:

MOV A, B    ; Load B into A
MOV B, C    ; Load C into B
MOV C, A    ; Load A (original B) into C

Real-World Tie:

• Khalti’s payment routing: When you transfer money, Khalti’s backend uses data transfer instructions to move amounts between temporary registers (e.g., MOV [temp_balance], AX) before updating the database.

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2.2 Arithmetic and Logic Instructions

Worked Example: Problem: Calculate (B + C) * 2 and store in A (8085). Solution:

ADD B       ; A = A + B (assume A=0 initially)
ADD C       ; A = A + C (now A = B + C)
ADD A       ; A = A + A (now A = (B + C) * 2)

Real-World Tie:

• NTC’s billing system: When calculating your phone bill, NTC’s server uses arithmetic instructions to sum call durations (e.g., ADD call_time, 5 for a 5-minute call) before applying taxes.

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2.3 Control Instructions: Branches and Calls

Key Instructions:

• Unconditional Jumps:
  • 8085: JMP 2000H
  • 8086: JMP 0x1234
• Conditional Jumps:
  • 8085: JZ label (jump if zero)
  • 8086: JNZ rel8 (jump if not zero)
• Subroutine Calls:
  • 8085: CALL 2000H (pushes PC onto stack)
  • 8086: CALL sub_routine

Worked Example: Problem: Write a loop to add numbers from 2000H to 2005H (8085). Solution:

LXI H, 2000H  ; HL = 2000H (start address)
MOV C, 0      ; Counter = 0
LOOP:         ; Label for loop
MOV A, M      ; A = [HL]
ADD C        ; A = A + C
MOV C, A      ; Update sum in C
INR L        ; HL++ (move to next address)
MVI A, 6     ; Compare HL with 2006H (end)
CPI          ; Compare A with 6 (2006H - 2000H = 6)
JNZ LOOP     ; Repeat if not zero

Real-World Tie:

• Pathao’s ride allocation: Pathao’s algorithm uses loops and conditional jumps to check driver availability (e.g., JNZ find_driver if no driver is free).

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3. Instruction Formats and Machine Cycles

3.1 8085 Instruction Format

Most 8085 instructions are 1-byte opcodes with optional operands:

• 1-byte: INR B (opcode 04H).
• 2-byte: MVI A, 50H (opcode 3EH + operand 50H).
• 3-byte: LDA 2050H (opcode 3AH + 16-bit address 2050H).

Machine Cycle Breakdown:

1. Fetch: PC outputs opcode to memory.
2. Decode: CPU decodes opcode.
3. Execute: Operands fetched (if needed), operation performed.
4. Writeback: Result stored (if applicable).

3.2 8086 Instruction Format

8086 uses variable-length instructions (1–6 bytes) with segment:offset addressing:

• Short: MOV AL, BL (2 bytes).
• Long: MOV AX, [BX+SI+10H] (6 bytes).

Example:

MOV AX, [BX+SI]  ; 6 bytes: opcode (88H) + ModR/M + displacement (0)

Real-World Tie:

• Bank loan calculations: When a bank processes your EMI, the server uses 8086’s segmented addressing to access large datasets (e.g., MOV AX, [DS:SI] fetches your loan amount from a 1MB table).

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4. Addressing Modes in Depth: Relative Addressing

Definition: The operand is an offset from the Program Counter (PC). Used in jumps and calls. Syntax:

• 8085: JNZ label (PC + offset).
• 8086: JMP rel8 (PC + signed 8-bit offset).

Worked Example: Problem: Calculate the effective address for JNZ label if:

• PC = 2000H
• label is at 2005H
• JNZ opcode is 2 bytes (C2H + offset).

Solution:

1. After fetching JNZ, PC = 2002H.
2. Offset = 2005H - 2002H - 2 (accounting for instruction length) = 1H.
3. Effective address = 2002H + 1H = 2003H (but PC is incremented by 2 first, so actual jump is to 2005H).

Real-World Tie:

• NEPSE stock trading: When a buy/sell order fails (e.g., insufficient funds), the system jumps to an error handler using relative addressing (e.g., JNZ insufficient_funds_label).

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5. Comparing 8085 and 8086 Addressing

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6. Common Pitfalls and Exam Tips

6.1 Relative Addressing Misconceptions

• Mistake: Assuming the offset is from the current PC value before the instruction is fetched.
• Correct Approach: The offset is calculated after the PC is incremented by the instruction length. Example: For JNZ label (2 bytes), PC points to the byte after the offset before jumping.

6.2 Instruction Set Gaps

• 8085 Limitation: No multi-byte arithmetic (e.g., ADD HL, DE is missing; must use DAD D for 16-bit add).
• 8086 Advantage: Supports 16-bit operations (ADD AX, BX) and segmented memory.

6.3 Worked Example Pitfalls

• Problem: Write code to load HL with 2000H in 8085.
• Wrong Answer: LXI H, 2000H (correct, but if you write LHLD 2000H, it loads HL from memory at 2000H, not sets HL to 2000H).
• Correct Answer:

  MVI H, 20H   ; High byte
  MVI L, 00H   ; Low byte
  

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In the Real World

1. eSewa’s Transaction Queue:

   • Idea Used: Indirect addressing (LHLD/SPHL).
   • How: When you pay a bill, eSewa’s server uses a stack pointer (SP) to dynamically access pending transactions. For example:

     PUSH H      ; Save HL (points to current transaction)
     LHLD 3000H  ; Load next transaction address into HL
     

   • Why: Indirect addressing allows eSewa to process thousands of transactions without hardcoding memory locations.

2. Daraz’s Order Fulfillment:

   • Idea Used: Register-indirect addressing (MOV A, M).
   • How: Daraz’s warehouse management system uses HL to traverse an order list stored in memory:

     LOOP: MOV A, M      ; A = [HL] (current order status)
     CPI 'D'            ; Check if delivered
     JNZ NOT_DONE       ; If not, process next
     INR L              ; Move to next order
     JMP LOOP
     

   • Why: Register-indirect addressing is faster than direct addressing for sequential data (e.g., orders in a linked list).

3. Ncell’s Call Duration Calculation:

   • Idea Used: Arithmetic instructions (ADD, INR).
   • How: Ncell’s billing server increments a counter for each minute of call:

     INR call_minutes  ; Increment call duration
     MOV A, call_minutes
     CPI 5             ; Check if >5 minutes
     JNZ CONTINUE      ; If not, keep adding
     

   • Why: Simple arithmetic instructions are energy-efficient for embedded systems like Ncell’s billing servers.

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Exam Tip

1. Define Precisely:

   • For relative addressing, always state: "The operand is an offset from the Program Counter (PC) after the instruction is fetched."
   • For data transfer instructions, specify source/destination (e.g., "LDA 2050H" loads memory at 2050H into the accumulator).

2. Trace Step-by-Step:

   • Examiners love register/memory traces. For LDA 2050H:

     Step	Action	Registers/Memory
     1	Fetch opcode 3A	PC = 2000H → 2001H
     2	Fetch address 2050H	PC = 2001H → 2003H
     3	Read memory at 2050H	A = [2050H]

3. Compare Architectures:

   • 8085: "Limited to 64KB memory; no segmented addressing."
   • 8086: "Uses segment:offset for 1MB addressing; supports 16-bit operations."

4. Real-World Applications:

   • Link indirect addressing to dynamic data (e.g., eSewa transactions).
   • Link arithmetic instructions to calculations (e.g., Ncell billing).
   • Link control instructions to loops/conditions (e.g., Pathao’s driver allocation).

5. Common Exam Questions:

   • "Why does 8086 use segmented addressing?" → Answer: To access 1MB memory (20-bit address bus) while maintaining backward compatibility with 16-bit registers.
   • "How does JNZ work in 8085?" → Answer: It adds the signed offset to the PC after the instruction is fetched, then jumps if the Zero flag is 0.

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Final Note: Master operand resolution (how addressing modes work) and instruction tracing (register/memory changes). Use real-world examples to remember concepts—e.g., think of eSewa’s indirect addressing for dynamic data or Ncell’s arithmetic for billing. Always draw diagrams for complex modes (e.g., segmented addressing in 8086) and trace instructions step-by-step in exams.