Counters & Registers: Design, Types, and Applications

TAKEAWAYS:

• Counters are sequential circuits that count pulses; asynchronous (ripple) counters use cascaded flip-flops with propagation delay, while synchronous counters update all bits simultaneously.
• Mod-N counters cycle through N unique states (e.g., mod-11 for timekeeping) and are designed using state diagrams and excitation tables.
• Shift registers (SISO, SIPO, PISO, PIP) store and shift data serially or in parallel, used in serial communication (UART), data conversion (ADC/DAC), and memory buffers.
• Parallel-in/parallel-out (PIPO) registers store n-bit data instantly, critical in CPU registers, ALUs, and cache memory.
• Practical applications include traffic light sequencing (mod-4 counter), Khalti transaction IDs (shift registers), and Ncell’s call duration timers (asynchronous counters).

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1. Counters: Basics and Classification

Counters are sequential circuits that increment or decrement in response to clock pulses. They are classified based on:

• Synchronization: Asynchronous (ripple) vs. synchronous.
• Counting direction: Up, down, or up-down.
• Modulus (N): Number of unique states (e.g., mod-10 for decimal).

1.1 Asynchronous (Ripple) Counters

• How it works: Each flip-flop’s output triggers the next flip-flop’s clock input (no global clock).
• Disadvantage: Propagation delay accumulates with each bit (slow for large n).
• Example: A 2-bit ripple counter using T-flip-flops:

  flowchart LR
    CLK["Clock"] --> T0["T-FF (Q0)"]
    T0 --> T1["T-FF (Q1)"]
    T1 --> Q1
    T0 --> Q0

  Timing diagram (for 4 pulses):

  | CLK | Q1 | Q0 |
  |-----|----|----|
  |  0  | 0  | 0  |
  |  1  | 0  | 1  |
  |  2  | 1  | 0  |
  |  3  | 1  | 1  |
  |  4  | 0  | 0  | (overflow)
  

1.2 Synchronous Counters

• How it works: All flip-flops share the same clock input; carry-lookahead logic reduces delay.
• Advantage: Faster (no ripple delay), but requires more gates.
• Example: 3-bit synchronous up-counter using T-flip-flops:
  • Excitation table (for T-flip-flops):

    Q2 Q1 Q0	T2	T1	T0
    000	1	1	1
    001	0	1	1
    010	0	0	1
    011	0	0	1
    100	0	0	1
    101	0	0	1
    110	0	0	1
    111	1	1	1

  • K-map for T2 (simplifies to T2 = Q2'Q1Q0):

  • Circuit:

1.3 Mod-N Counters

• Definition: Counters that cycle through N states (e.g., mod-11 for a digital clock’s seconds).
• Design steps:
  1. Draw the state diagram (e.g., for mod-5: 0→1→2→3→4→0).
  2. Derive the excitation table (for T-flip-flops: T = Q⊕Q_next).
  3. Simplify using K-maps.
• Example: Mod-7 counter (state diagram):

  stateDiagram-v2
    [*] --> 0
    0 --> 1
    1 --> 2
    2 --> 3
    3 --> 4
    4 --> 5
    5 --> 6
    6 --> [*]

  • Excitation table (for 3-bit mod-7):

    Q2 Q1 Q0	Q2+ Q1+ Q0+	T2	T1	T0
    000	001	0	0	1
    001	010	0	1	1
    010	011	0	0	1
    011	100	1	1	1
    100	101	0	0	1
    101	110	0	1	1
    110	000	1	1	1

  • Simplified T2: T2 = Q2'Q1Q0 + Q2Q1'Q0' (from K-map).

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2. Registers: Storage and Data Movement

Registers store n-bit data and perform operations like shifting, loading, or parallel transfer.

2.1 Parallel-In/Parallel-Out (PIPO) Register

• Function: Stores n bits in parallel and outputs them in parallel.
• Example: 4-bit PIPO register (using D-flip-flops):

  flowchart LR
    D0["D0"] --> FF0["D-FF (Q0)"]
    D1["D1"] --> FF1["D-FF (Q1)"]
    D2["D2"] --> FF2["D-FF (Q2)"]
    D3["D3"] --> FF3["D-FF (Q3)"]
    CLK["Clock"] --> FF0 --> FF1 --> FF2 --> FF3

• Applications:
  • CPU registers (e.g., AX, BX in x86).
  • Memory buffers in data transfer (e.g., USB controllers).

2.2 Shift Registers

Shift registers move data serially (bit-by-bit) or in parallel. Types:

1. SISO (Serial-In-Serial-Out): Shifts data in/out serially (e.g., delay lines).
2. SIPO (Serial-In-Parallel-Out): Converts serial data to parallel (e.g., ADC input).
3. PISO (Parallel-In-Serial-Out): Converts parallel to serial (e.g., UART transmission).
4. PIPO (Parallel-In-Parallel-Out): Stores data instantly (e.g., cache memory).

• Example: 3-bit SIPO shift register (using D-flip-flops):

  flowchart LR
    D["Serial In"] --> FF0["D-FF (Q0)"]
    FF0 --> FF1["D-FF (Q1)"]
    FF1 --> FF2["D-FF (Q2)"]
    CLK["Clock"] --> FF0 --> FF1 --> FF2
    FF0 --> Q0["Q0"]
    FF1 --> Q1["Q1"]
    FF2 --> Q2["Q2"]

  Timing diagram (for input 101):

  | CLK | D  | Q2 | Q1 | Q0 |
  |-----|----|----|----|----|
  |  0  |  1 |  0 |  0 |  0 |
  |  1  |  0 |  1 |  0 |  0 |
  |  2  |  1 |  0 |  1 |  0 |
  |  3  | x  |  1 |  0 |  1 |
  

2.3 Bidirectional Shift Registers

• Function: Shifts data left or right based on a control signal.
• Example: 4-bit bidirectional register (using MUXes):

  flowchart LR
    D0["D0"] --> M0["MUX (Q0)"]
    Q1["Q1"] --> M0
    M0 --> FF0["D-FF"]
    D1["D1"] --> M1["MUX (Q1)"]
    Q0 --> M1
    M1 --> FF1["D-FF"]
    CLK["Clock"] --> FF0 --> FF1 --> FF2 --> FF3

• Applications:
  • Data encryption (e.g., shifting bits in AES).
  • Serial communication (e.g., Khalti’s transaction ID generation).

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3. Practical Applications in Nepal

3.1 Asynchronous Counters in Traffic Lights

• System: Kathmandu’s traffic lights use mod-4 counters (red→yellow→green→red).
• Design:
  • State sequence: 00 (Red) → 01 (Yellow) → 10 (Green) → 11 (Red).
  • Flip-flops: 2-bit ripple counter with T-flip-flops.
  • Timing: Each state lasts 30 seconds (controlled by an external timer).

3.2 Shift Registers in Khalti Payments

• Process: When you scan a QR code, Khalti generates a 16-digit transaction ID.
• How shift registers help:
  • A 16-bit SIPO register converts the serial data from the card reader into parallel bits for processing.
  • A bidirectional shift register may be used to validate the ID by shifting and comparing bits.

3.3 Ncell’s Call Duration Timer

• Problem: Ncell needs to track call duration (up to 9999 seconds).
• Solution: A 12-bit synchronous counter (4 bits per digit) with a mod-10000 design.
• Why synchronous?:
  • Avoids ripple delay (critical for billing accuracy).
  • Uses carry-lookahead logic for faster updates.

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4. Comparison: Asynchronous vs. Synchronous Counters

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5. Real-World Chips and ICs

5.1 74LS93: 4-bit Asynchronous Counter

• IMAGE: "74LS93 IC pinout" | A 14-pin DIP chip with async count inputs.
• Features:
  • Asynchronous clear (active low).
  • Ripple carry-out (Q3 → next stage).
  • Used in digital clocks, timers.

5.2 74LS194: 4-bit Bidirectional Shift Register

• IMAGE: "74LS194 IC pinout" | A 16-pin DIP with parallel load and shift controls.
• Features:
  • Parallel load (for instant data entry).
  • Left/right shift (controlled by S0, S1).
  • Used in serial communication (UART), data encryption.

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Exam Tip

1. Design questions:

   • Always draw the state diagram first for mod-N counters.
   • For asynchronous counters, show the ripple delay in the timing diagram.
   • For synchronous counters, derive the excitation table and simplify using K-maps.

2. Common pitfalls:

   • Forgetting to reset the counter (e.g., mod-5 counter must return to 000).
   • Misplacing clock inputs (asynchronous counters use Q as clock for next FF).
   • Ignoring load enable in shift registers (e.g., LD signal in 74LS194).

3. Short-answer tips:

   • Asynchronous vs. synchronous: Mention speed (ripple delay) and power (synchronous uses more gates).
   • Shift registers: Link to serial communication (e.g., "SIPO converts serial data to parallel for ADC").

4. Diagrams:

   • Timing diagrams must show clock edges and output transitions.
   • State diagrams must be complete (all states and transitions).

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Worked Example: Design a Mod-11 Up Counter

Problem: Design a 4-bit synchronous mod-11 counter using T-flip-flops. Solution:

1. State diagram:

   stateDiagram-v2
     [*] --> 0000
     0000 --> 0001
     0001 --> 0010
     0010 --> 0011
     0011 --> 0100
     0100 --> 0101
     0101 --> 0110
     0110 --> 0111
     0111 --> 1000
     1000 --> 1001
     1001 --> [*]

2. Excitation table (for T-flip-flops):

   Q3 Q2 Q1 Q0	Q3+ Q2+ Q1+ Q0+	T3	T2	T1	T0
   0000	0001	0	0	0	1
   0001	0010	0	0	1	1
   0010	0011	0	0	0	1
   0011	0100	0	1	1	1
   0100	0101	0	0	0	1
   0101	0110	0	0	1	1
   0110	0111	0	0	0	1
   0111	1000	1	1	1	1
   1000	1001	0	0	0	1
   1001	0000	1	1	1	1

3. Simplified T3 (from K-map):
   • Circuit:

4. Timing diagram (first 3 cycles):

   | CLK | Q3 Q2 Q1 Q0 |
   |-----|-------------|
   |  0  |  0000       |
   |  1  |  0001       |
   |  2  |  0010       |
   |  3  |  0011       |
   

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In the Real World

1. eSewa’s Transaction Counter

   • Idea: Mod-9999 counter (for transaction IDs).
   • How: A 12-bit synchronous counter (4 bits per digit) ensures unique IDs. When the counter reaches 9999, it resets to 0000 (mod-10000 behavior).
   • Why synchronous? Avoids delay in high-volume transactions.

2. Pathao’s Ride Distance Meter

   • Idea: Up-down counter (for odometer-like distance tracking).
   • How: A 16-bit bidirectional counter increments for distance traveled and decrements for route corrections. Uses carry-lookahead logic for accuracy.
   • Real chip: Similar to the 74LS190 (up-down counter IC).

3. NTC’s Electricity Meter

   • Idea: Asynchronous ripple counter for pulse counting.
   • How: Each pulse from the meter corresponds to 1 unit of electricity. A 4-digit BCD ripple counter (using 74LS90) displays the total consumption.
   • Why ripple? Low power consumption is critical for long-term operation.

4. WhatsApp’s Message Queue

   • Idea: Shift registers for buffering messages.
   • How: When you send a message, it’s stored in a FIFO buffer (implemented with shift registers) before transmission. The buffer ensures messages are sent in order even if the network is slow.
   • Example: A 32-bit SIPO register converts your typed message (serial data) into parallel bits for processing.

5. NEPSE Stock Ticker

   • Idea: Parallel-in/parallel-out registers for real-time data.
   • How: Stock prices are fetched in parallel and stored in PIPO registers (e.g., 16-bit registers for price and volume). This allows instant display on screens without serial delay.
   • Real chip: 74LS374 (octal D-type transparent latch, used in display interfaces).