Flip-Flops, Latches & Sequential Logic Fundamentals

1. Sequential Circuits vs. Combinational Circuits

Sequential circuits remember past inputs (state) and produce outputs based on both current inputs and stored state. Unlike combinational circuits (e.g., adders, multiplexers), they have memory elements (flip-flops/latches) and timing constraints (clock signals).

flowchart LR
    A["Combinational Circuit"] -->|"No memory"| B["Output depends only on current inputs"]
    C["Sequential Circuit"] -->|"Has memory"| D["Output depends on current inputs + stored state"]
    D --> E["Flip-flops/Latches"]
    D --> F["Clock signal"]

Key difference:

2. Latches: Basic Memory Elements

Latches are level-sensitive (output changes when input level changes) and asynchronous (no clock). Two types:

A. SR Latch (Set-Reset)

• Inputs: S (Set), R (Reset)
• Outputs: Q, Q̅ (complement)
• Forbidden state: S=R=1 (race condition → undefined output).

Truth Table:

Circuit Diagram:

Worked Example: Design a latch to turn on a streetlight (Q=1) when a sensor (S=1) detects darkness, and turn it off (Q=0) when a switch (R=1) is pressed. Solution:

• Use an SR latch with S connected to the sensor and R to the switch.
• Timing: Output changes immediately when S or R changes (no clock).

B. D Latch (Delay/Transparent Latch)

• Input: D (data)
• Output: Q = D when Enable=1; holds last D when Enable=0.
• Used in: Data holding, transparent memory.

Truth Table:

Circuit:

Real-World Tie-In: eSewa’s Payment Verification When you pay via eSewa, the system uses latches to hold your transaction data (D) until the bank confirms (Enable=1). Once confirmed, the latch updates (Q=1 for success) and holds the state until you log out.

3. Flip-Flops: Clocked Memory Elements

Flip-flops are edge-triggered (output changes only at clock edges) and synchronous (all flip-flops update simultaneously). Four types:

A. SR Flip-Flop

• Derived from SR latch but clocked.
• Forbidden state: S=R=1 at clock edge.
• Uses: Simple state storage.

Characteristic Table (shows next state Q+):

Excitation Table (shows required S, R for desired Q+):

B. D Flip-Flop

• Input: D (data)
• Output: Q = D at clock rising edge.
• Advantage: No forbidden state; simpler design.

Truth Table:

Worked Example: Design a 1-bit register using a D flip-flop to store a bit from a sensor. Solution:

• Connect sensor output to D.
• Q holds the last sensor value at each clock tick.

Real-World Tie-In: Ncell’s Call Duration Counter Ncell’s billing system uses D flip-flops to store call duration data (D) at each second (clock). The output Q accumulates the total duration for billing.

C. T Flip-Flop (Toggle)

• Input: T (toggle)
• Output: Q toggles (Q̅) when T=1 at clock edge.
• Uses: Counters, frequency dividers.

Truth Table:

Worked Example: Design a toggle switch circuit for a traffic light. Solution:

• Use a T flip-flop with T=1 (always toggle).
• Q alternates between 0 (red) and 1 (green) at each clock pulse.

Timing Diagram:

D. JK Flip-Flop (Universal Flip-Flop)

• Inputs: J (set), K (reset)
• No forbidden state: J=K=1 → toggle.
• Most versatile: Can emulate SR, D, T flip-flops.

Characteristic Table:

Excitation Table:

Worked Example: Convert a JK flip-flop to a D flip-flop. Solution:

• Connect J = D, K = Q̅ (complement of Q).
• Now Q+ = D at clock edge.

Real-World Tie-In: Khalti’s Transaction Lock Khalti uses JK flip-flops to lock transactions:

• J=1 (set) when a payment is initiated.
• K=1 (reset) only after bank confirmation.
• J=K=1 toggles the state if a timeout occurs (retry).

4. Flip-Flop Comparisons

Advantages of JK over SR:

• No race condition.
• Can toggle (J=K=1).
• More flexible for design.

5. Master-Slave Flip-Flops

• Problem: Clock skew in single flip-flops.
• Solution: Master-slave configuration:
  • Master captures input at clock rising edge.
  • Slave outputs data at clock falling edge.
• Result: No glitches; stable output.

Circuit:

Timing Diagram:

Real-World Tie-In: Pathao’s Ride Allocation Pathao’s server uses master-slave flip-flops to allocate rides:

• Master: Captures rider request at clock tick.
• Slave: Assigns driver only after confirmation (falling edge).

6. Flip-Flop Applications

A. State Storage

• Example: Traffic light controller (red → green → yellow → repeat).
• Circuit: Use JK flip-flops with J=K=1 (toggle) and decode outputs for lights.

B. Counters

• Example: 4-bit binary counter using T flip-flops.
  • Each flip-flop toggles when previous output is 1.
  • Timing Diagram:

  Q0-Q3 toggling sequentially. (Image: Lambtron, CC BY-SA 4.0, via Wikimedia Commons) ```

Real-World Tie-In: NTC’s Electricity Meter NTC’s meters use flip-flop counters to track units consumed:

• Each pulse (from sensor) toggles a flip-flop.
• Output Q accumulates total units.

C. Registers

• Example: 8-bit register using D flip-flops.
  • Each bit stored in a D flip-flop.
  • Parallel load: All flip-flops update at same clock edge.

Circuit:

flowchart LR
    A["Clock"] --> B["D0"]
    A --> C["D1"]
    A --> D["D7"]
    B --> E["Q0"]
    C --> F["Q1"]
    D --> G["Q7"]
    E --> H["Output Bus"]
    F --> H
    G --> H

7. Asynchronous vs. Synchronous Flip-Flops

8. Exam Tip: How to Score Full Marks

1. Draw circuits correctly:

   • Use standard gate symbols (no AND/OR symbols for flip-flops).
   • Label clock, inputs, outputs, and states clearly.
   • Example: For a JK flip-flop, show J, K, CLK, Q, Q̅.

2. Show all tables:

   • Characteristic table (next state).
   • Excitation table (required inputs for desired state).
   • Truth table (if combinational logic is involved).

3. Timing diagrams:

   • Draw clock, inputs, and outputs on the same timeline.
   • Mark rising/falling edges and state changes.
   • Example: For a counter, show how outputs toggle.

4. Real-world connections:

   • Link designs to eSewa (latches), Ncell (flip-flops), or NTC (counters).
   • Example: "This JK flip-flop can be used in Khalti’s payment lock mechanism..."

5. Common pitfalls:

   • Forgetting forbidden states in SR flip-flops.
   • Misplacing clock edges in timing diagrams.
   • Not showing feedback paths in sequential circuits.

Past Exam Question Analysis: Question: "Design a 2-bit asynchronous binary counter using T flip-flops." Expected Answer:

1. Circuit:
   • Two T flip-flops (FF0, FF1).
   • FF0.T = 1 (always toggle).
   • FF1.T = Q0 (toggle only when Q0=1).
2. Timing Diagram:
   • Show Q0, Q1 toggling sequentially.
3. State Table:

   Q1	Q0	Next State
   0	0	01
   0	1	10
   1	0	11
   1	1	00

Real-World Tie-In: Daraz’s Order Queue Daraz’s order processing uses asynchronous counters (like this 2-bit design) to track pending orders:

• Each order toggles FF0.
• When Q0=1 and Q1=1, the system resets (order fulfilled).