8085 Timing, Control & Memory Interfacing: DMA, Cycles, I/O Mapping

Core Concepts: Timing and Control Signals

1. Machine Cycles vs. Instruction Cycles

The 8085 microprocessor executes instructions through machine cycles, which are the fundamental operations it performs to fetch or execute data. Each instruction is broken into one or more machine cycles. There are four types of machine cycles in the 8085:

stateDiagram-v2
    [*] --> OP_FETCH: Opcode Fetch
    OP_FETCH --> MEM_READ: Memory Read
    MEM_READ --> OP_DECODE: Opcode Decode
    OP_DECODE --> EXECUTE: Execute (Fetch Operand/Write Memory)
    EXECUTE --> [*]

• Opcode Fetch (M1): The CPU fetches the opcode from memory.
• Memory Read (M): The CPU reads data from memory (e.g., for LDA).
• Memory Write (M): The CPU writes data to memory (e.g., for STA).
• I/O Read/Write (I): The CPU interacts with I/O devices.

Worked Example: Timing for MVI A, 32H The instruction MVI A, 32H (Move Immediate to A) requires three machine cycles:

1. Opcode Fetch (M1): Fetch MVI opcode (0x3E).
2. Memory Read (M): Fetch the operand 32H.
3. Execute (M): Load 32H into the accumulator (A).

Timing Diagram for MVI A, 32H:

(Note: The diagram should show T-states, ALE, RD, WR, IO/M, and S0-S1 signals.)

2. Control Signal Generation

The 8085 generates control signals (RD, WR, IO/M, S0, S1, ALE, HLDA, HOLD) to coordinate operations. These signals are derived from the instruction register (IR) and timing and control unit (TCU).

Key Control Signals:

Logic Diagram for Control Signals:

Direct Memory Access (DMA)

1. What is DMA?

DMA (Direct Memory Access) allows high-speed peripherals (e.g., disk drives, network cards) to transfer data directly to/from memory without CPU intervention. This reduces CPU overhead and improves system performance.

2. DMA Controller (8237 DMAC)

The 8237 DMAC manages DMA transfers. It has:

• 4 independent channels (for 4 peripherals).
• Address and word count registers (store memory address and transfer count).
• Control registers (configure transfer mode, direction, and priority).

Internal Block Diagram of 8237 DMAC:

*(Note: The diagram should show:

• Address Registers (for source/destination memory).
• Word Count Registers (number of bytes to transfer).
• Control Registers (mode, priority, direction).
• Data Bus Buffer (temporary storage for data).
• Request and Acknowledge Logic (HRQ, HLDA).)*

3. DMA Transfer Process

1. Peripheral requests DMA by asserting HRQ (Hold Request).
2. CPU acknowledges by asserting HLDA (Hold Acknowledge) and releases the bus.
3. DMAC takes control, transfers data directly between memory and peripheral.
4. CPU resumes after transfer completes.

Timing Diagram for DMA Transfer:

```figure
{"type":"timeline","events":[{"date":"T1","label":"DMA Request (HRQ)"},{"date":"T2","label":"HOLD asserted"},{"date":"T3","label":"HLDA acknowledged"},{"date":"T4","label":"DMA takes bus control"},{"date":"T5","label":"Data transfer begins"},{"date":"T6","label":"DMA release bus (HOLD deasserted)"}],"caption":"Simplified DMA Handshake Timing (8085 + 8237)"}

*(Note: The diagram should show:

• HRQ (rising edge) → HLDA (CPU releases bus).
• DREQ (DMA Request) → DACK (DMA Acknowledge).
• Data transfer on D0-D7 during T-states.)*

4. DMA Modes

Memory Interfacing

1. Memory Addressing in 8085

The 8085 has a 16-bit address bus, allowing access to 64KB (65,536 bytes) of memory. The address is split into:

• Lower 8 bits (A0-A7): Latched by ALE into a latch (e.g., 74LS373).
• Upper 8 bits (A8-A15): Directly connected to memory.

Memory Interfacing Circuit:

*(Note: The diagram should show:

• 8085 CPU with A0-A15, ALE, RD, WR.
• 74LS373 latch for lower 8 bits.
• Memory chip (e.g., 2114 SRAM) with address, data, and control lines.)*

2. Memory Read/Write Timing

• Read Cycle:

  1. CPU places address on bus.
  2. ALE latches lower 8 bits.
  3. RD goes low → memory sends data.
  4. CPU reads data on T3 state.

• Write Cycle:

  1. CPU places address and data on bus.
  2. ALE latches address.
  3. WR goes low → memory stores data.

Timing Diagram for Memory Read/Write:

(Note: The diagram should show T1-T4 states with ALE, RD, WR, and data transitions.)

I/O Interfacing: Isolated vs. Memory-Mapped I/O

1. Isolated I/O (8085 Default)

• Uses dedicated I/O instructions (IN, OUT).
• Separate address space for I/O devices (8-bit ports).
• Advantages:
  • Simple wiring (only 8 address lines for I/O).
  • No memory address space wasted.
• Disadvantages:
  • Slower than memory-mapped (extra instructions).
  • Limited to 256 I/O ports.

Example:

IN 30H    ; Read from port 30H (e.g., keyboard)
OUT 31H   ; Write to port 31H (e.g., printer)

2. Memory-Mapped I/O

• I/O devices are treated as memory locations.
• Uses memory access instructions (LDA, STA).
• Advantages:
  • Faster (uses memory instructions).
  • More flexible (can use all memory instructions).
• Disadvantages:
  • Wastes memory address space.
  • Requires decoding logic to distinguish I/O from memory.

Example:

LDA 8000H  ; Read from device at 8000H (e.g., UART)
STA 8001H  ; Write to device at 8001H

In the Real World

1. eSewa and Kathmandu Traffic Management (DMA)

• eSewa processes thousands of online transactions per second. Behind the scenes, DMA controllers in servers transfer data between high-speed SSDs and RAM without CPU intervention, ensuring fast payment processing.
• Kathmandu Traffic Management System uses embedded microprocessors (like the 8085’s principles) to read sensor data (e.g., traffic cameras) via memory-mapped I/O. The CPU decodes signals from ports (e.g., IN instructions) to adjust traffic lights dynamically.

2. Ncell and NTC: DMA in Data Transfer

• Ncell’s 4G/5G base stations use DMA to transfer large data packets between modems and RAM without CPU delays. This is critical for handling calls and internet traffic efficiently.
• NTC’s fiber-optic networks rely on DMA-like mechanisms in routers to forward data packets directly to memory buffers, reducing latency in high-speed communications.

3. Banking Systems (Memory Interfacing)

• When you transfer money via Khalti or eSewa, the backend server reads/writes transaction data to memory-mapped I/O ports (e.g., database interfaces). The 8085’s memory interfacing principles apply here: the CPU must correctly time RD/WR signals to ensure data integrity during transfers.

Exam Tip

1. Timing Diagrams: Always label T-states (T1-T4), ALE, RD, WR, and IO/M signals. For MVI A, 32H, show 3 machine cycles (Opcode Fetch, Memory Read, Execute).
2. DMA Questions: Focus on the 8237 DMAC block diagram and timing handshake (HRQ, HLDA, DREQ, DACK). Compare DMA vs. programmed I/O (speed, CPU involvement).
3. Control Signals: Know how S0-S1 decode into RD, WR, and IO/M. Draw the logic diagram for control signal generation.
4. I/O Mapping:
   • Isolated I/O: Uses IN/OUT instructions, 8-bit ports.
   • Memory-Mapped: Uses LDA/STA, wastes memory space but is faster.
5. Common Mistakes:
   • Forgetting ALE latches the lower 8 bits of the address.
   • Mislabeling RD/WR in timing diagrams (active low!).
   • Confusing machine cycles (M1, M, I) with T-states (clock pulses).

Practice Questions:

1. Draw the timing diagram for STA 2050H and explain the role of ALE.
2. Compare block DMA and demand DMA with examples.
3. Design a circuit to interface the 8085 with a 2KB memory chip (e.g., 2114 SRAM). Show address decoding logic.
4. Why is memory-mapped I/O preferred in modern systems despite its disadvantages?