System Buses, Multiplexing, and Advanced Interfacing

TAKEAWAYS:

• System buses are the communication highways between CPU, memory, and I/O devices, classified into data, address, and control buses with distinct roles and directions.
• Multiplexing combines multiple signals (e.g., address/data) onto a single bus to save pins, critical in microprocessors like the 8085.
• Bus arbitration resolves conflicts when multiple devices compete for the bus, using techniques like daisy-chaining or priority encoders.
• Direct Memory Access (DMA) allows peripherals to transfer data directly to/from memory without CPU intervention, improving efficiency.
• Advanced topics include bus expansion (e.g., ISA, PCI slots) and system performance optimization via bus width, clock speed, and pipelining.

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System Buses: The Backbone of Computer Communication

A system bus is a shared communication pathway that connects the CPU, memory, and I/O devices. It enables data transfer between components by carrying three types of signals:

1. Data Bus (Bidirectional)

• Purpose: Transfers actual data (instructions, operands) between CPU, memory, and I/O.
• Direction: Bidirectional (CPU can send/receive data).
• Width: Determines data transfer rate (e.g., 8-bit, 16-bit, 32-bit).
• Example: In an 8086 microprocessor, the data bus is 16 bits wide, allowing 2 bytes of data to be transferred at once.

![8086 microprocessor pinout diagram](/media/02bc5585c1b8648d2473.png "Labelled pinout showing data bus (D0-D15), address bus (A0-A19), and control signals. (Image: lamfe, CC0, via Wikimedia Commons)")

2. Address Bus (Unidirectional)

• Purpose: Specifies the memory location or I/O device the CPU wants to access.
• Direction: Unidirectional (CPU sends addresses; memory/I/O responds).
• Width: Determines maximum addressable memory (e.g., 16-bit address bus = 64 KB memory).
• Example: The 8085 has a 16-bit address bus, addressing up to 64 KB of memory.

3. Control Bus (Bidirectional)

• Purpose: Coordinates operations (e.g., read/write signals, interrupts, clock sync).
• Direction: Bidirectional (CPU sends control signals; devices respond).
• Key Signals:
  • Read (RD): CPU reads data from memory/I/O.
  • Write (WR): CPU writes data to memory/I/O.
  • Memory Request (MREQ): Indicates memory access.
  • I/O Request (IO/M): Differentiates memory vs. I/O access.

```figure
{"type":"layers","layers":["System Bus","CPU","Memory","I/O Devices"],"right":["Data Bus (Bidirectional)","Address Bus (Unidirectional)","Control Bus (Bidirectional)"],"highlight":["System Bus"],"caption":"Interaction between CPU, memory, and I/O devices via the system bus (data, address, and control buses)."}

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Multiplexing: Combining Buses for Efficiency

In microprocessors like the 8085, the address and data buses are multiplexed onto the same pins to reduce pin count and lower cost. This is done using a multiplexer (MUX) controlled by the ALE (Address Latch Enable) signal.

How Multiplexing Works in 8085:

1. First Cycle (Address Phase):

   • CPU places the 16-bit address on the AD0-AD7 pins (lower 8 bits) and A8-A15 pins (upper 8 bits).
   • ALE signal goes high, latching the address into an address latch (e.g., 74LS373).
   • The latched address is then placed on the address bus (A0-A15).

2. Second Cycle (Data Phase):

   • The AD0-AD7 pins are switched to data bus mode.
   • Data is transferred between CPU and memory/I/O.

```mermaid
sequenceDiagram
    participant CPU
    participant AD0-AD7 as AD Bus (Multiplexed)
    participant ALE
    participant AddressLatch
    participant Memory

    CPU->>AD0-AD7: Place Address (Lower 8 bits)
    CPU->>ALE: High (Latch Enable)
    AD0-AD7->>AddressLatch: Latch Address
    CPU->>AD0-AD7: Release (Switch to Data Mode)
    CPU->>Memory: Read/Write Data via AD0-AD7

Why Multiplexing?

• Reduces Pin Count: Combines address and data buses (e.g., 8085 uses 16 pins for both).
• Cost-Effective: Fewer pins mean cheaper packaging.
• Flexibility: Allows dynamic use of pins for different purposes.

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Bus Arbitration: Resolving Conflicts

When multiple devices (e.g., CPU, DMA controller, I/O devices) compete for the bus, bus arbitration ensures only one device uses the bus at a time. Common methods:

1. Daisy-Chaining (Linear Arbitration)

• Devices are connected in a chain.
• The bus request (BR) and bus grant (BG) signals propagate through the chain.
• The first device with a pending request gets the bus.

```figure
{"type":"network","nodes":["CPU","DMA Controller","I/O Device 1","I/O Device 2"],"edges":[["CPU","DMA Controller",{"label":"BR/BG"}],["DMA Controller","I/O Device 1",{"label":"BR/BG"}],["I/O Device 1","I/O Device 2",{"label":"BR/BG"}]],"directed":true,"caption":"Daisy-chaining arbitration: Devices connected in a chain, with BR/BG signals propagating sequentially."}

2. Priority Encoder

• Devices have fixed priorities (e.g., CPU > DMA > I/O).
• A priority encoder grants the bus to the highest-priority requesting device.

3. Centralized Arbitrator

• A dedicated bus arbiter (e.g., 8289) evaluates requests and grants the bus.

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Direct Memory Access (DMA): Bypassing the CPU

DMA allows high-speed peripherals (e.g., hard drives, network cards) to transfer data directly to/from memory without CPU intervention. This reduces CPU overhead and improves performance.

How DMA Works:

1. DMA Request: Peripheral sends a DMA request (HRQ) to the DMA controller.
2. Bus Grant: DMA controller requests the bus from the CPU (via HLDA).
3. Data Transfer: DMA controller takes control of the bus and transfers data directly to/from memory.
4. Completion: DMA controller signals the CPU and peripheral when transfer is done.

```mermaid
sequenceDiagram
    participant Peripheral
    participant DMAController
    participant CPU
    participant Memory

    Peripheral->>DMAController: DMA Request (HRQ)
    DMAController->>CPU: Bus Request (HOLD)
    CPU-->>DMAController: Bus Grant (HLDA)
    DMAController->>Memory: Transfer Data (Direct)
    DMAController->>Peripheral: Transfer Complete
    DMAController->>CPU: Release Bus

Example: Hard Disk Data Transfer

• When you copy a file in Windows, the hard disk controller uses DMA to transfer data directly to RAM without the CPU handling every byte.
• This is why large file transfers don’t freeze your system.

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Bus Expansion and Standards

Modern systems use expansion buses to add peripherals. Key standards:

![PCIe slot and expansion card](/media/4e2853e97599c3b54928.jpg "A labelled photo of a PCIe slot on a motherboard with a graphics card inserted. (Image: The original uploader was Smial at German Wikipedia., CC BY-SA 2.0 de, via Wikimedia Commons)")

Why PCIe Replaced PCI?

• Serial vs. Parallel: PCIe uses serial lanes (less crosstalk, higher speeds).
• Scalability: Supports 1 to 32 lanes (e.g., x16 for GPUs).
• Power Efficiency: Lower voltage requirements.

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Real-World Applications

1. eSewa and Kathmandu Traffic Management

• Problem: eSewa processes thousands of transactions per second. Without efficient bus arbitration, the system would bottleneck.
• Solution: Modern servers use PCIe buses for high-speed data transfer between the CPU, RAM, and storage (SSDs). The DMA controller ensures fast data movement without CPU delays.
• Example: When you pay a bill on eSewa, your transaction data travels via PCIe lanes from your phone (via mobile network) to eSewa’s servers, where DMA controllers handle bulk data transfers to databases.

2. Pathao’s Ride-Matching Algorithm

• Problem: Pathao’s servers must match riders and drivers in milliseconds. Slow bus communication would cause delays.
• Solution: Pathao’s cloud servers use high-speed PCIe buses and DMA to transfer data between:
  • CPU (processing requests)
  • RAM (storing user locations)
  • SSDs (logging trips)
• Example: When you request a ride, your GPS location is sent via PCIe to the server’s RAM, where DMA transfers it to the matching algorithm’s working memory.

3. NTC’s Fiber-Optic Network Backbone

• Problem: Nepal’s telecom network (NTC) handles millions of calls and internet packets daily. Traditional buses would be too slow.
• Solution: NTC uses fiber-optic cables (not a bus, but analogous in principle) with high-speed serial communication (like PCIe). Routers use bus arbitration to manage data packets between different network interfaces.
• Example: When you call someone on Ncell, your voice data travels through optical fibers (like a super-fast bus) and is routed via DMA-like mechanisms in the router to reach the destination.

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Worked Example: 8085 Bus Multiplexing Trace

Scenario: The 8085 CPU reads data from memory location 2050H. Trace the bus signals.

1. Address Phase:

   • CPU places address 2050H on AD0-AD7 (lower 8 bits: 50H) and A8-A15 (upper 8 bits: 20H).
   • ALE goes high, latching 2050H into the address latch.
   • A0-A15 now holds 2050H.

2. Data Phase:

   • AD0-AD7 switch to data mode.
   • CPU asserts RD (read signal).
   • Memory at 2050H places data on AD0-AD7.
   • CPU reads the data.

```figure
{"type":"timeline","events":[{"label":"CPU places address (2050H) on AD0-AD15","color":"#3498db"},{"label":"ALE high: Latch address into 74LS373","color":"#2ecc71"},{"label":"AD0-AD7 switch to data mode","color":"#e74c3c"},{"label":"RD asserted: Memory reads data","color":"#f39c12"},{"label":"CPU reads data from AD0-AD7","color":"#9b59b6"}],"caption":"Step-by-step bus multiplexing trace for 8085 reading from memory location 2050H."}

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Advanced Topics: Bus Performance Optimization

1. Bus Width

• Wider buses (e.g., 64-bit vs. 32-bit) transfer more data per cycle.
• Example: A 64-bit CPU can read 8 bytes in one cycle vs. 4 bytes on a 32-bit bus.

2. Clock Speed

• Higher clock speeds allow more transfers per second.
• Example: PCIe 4.0 runs at 16 GT/s (vs. PCIe 3.0’s 8 GT/s).

3. Pipelining

• Overlaps bus operations (e.g., fetch, decode, execute) to hide latency.
• Example: Modern CPUs use pipelined buses to keep the data bus active while the address bus is being used.

4. Burst Mode

• Transfers multiple data items in a single bus cycle (e.g., graphics cards).
• Example: A GPU uses burst mode to transfer texture data in chunks.

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Exam Tip: How to Score Full Marks

1. Define Clearly: Always start with definitions (e.g., "A system bus is a shared communication pathway...").
2. Use Diagrams: Draw bus structures, multiplexing traces, or arbitration chains to visualize answers.
3. Compare Tables: For bus standards (ISA, PCI, PCIe), use a comparison table with width, speed, and use cases.
4. Real-World Links: Relate multiplexing to 8085, DMA to hard drives, and arbitration to eSewa/Khalti servers.
5. Trace Signals: For questions on 8085, show ALE timing, address latching, and data phase steps.
6. Avoid Vague Terms: Instead of "fast bus," say "PCIe 4.0 with 16 GT/s bandwidth."
7. Highlight Keywords: Examiners love terms like:
   • "Bidirectional data bus"
   • "Unidirectional address bus"
   • "Daisy-chaining arbitration"
   • "DMA controller bypasses CPU"

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Common Pitfalls to Avoid

• Confusing Unidirectional/Bidirectional: The address bus is always unidirectional; data and control buses are bidirectional.
• Multiplexing Missteps: Forgetting that ALE latches the address before switching to data mode.
• DMA vs. Interrupts: DMA is for bulk data; interrupts are for event-driven tasks.
• Bus Standards Mix-Up: PCI is parallel; PCIe is serial. Don’t confuse them!
• Overlooking Control Signals: Always mention RD, WR, MREQ, and IO/M in memory/I/O questions.

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Summary Table: Key Concepts

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Practice Questions (Exam-Style)

1. Explain why the 8085 uses multiplexing for its address and data buses. Draw a timing diagram showing the ALE signal and data transfer.

   • Hint: Focus on pin reduction, cost, and the two-phase cycle (address latch → data transfer).

2. Compare ISA, PCI, and PCIe buses in a table. Which would you use for a high-end gaming PC, and why?

   • Hint: Emphasize serial vs. parallel, bandwidth, and scalability.

3. Trace the steps a DMA controller takes to transfer data from a hard disk to RAM. Include bus request/grant signals.

   • Hint: Use a sequence diagram with CPU, DMA controller, and memory.

4. Why is the address bus unidirectional, while the data bus is bidirectional? Provide examples from the 8086.

   • Hint: Addresses are only sent by the CPU; data flows both ways.

5. How does bus arbitration ensure only one device uses the bus at a time? Draw a daisy-chaining arbitration circuit.

   • Hint: Show BR (bus request) and BG (bus grant) signals propagating through devices.