Memory & I/O Interfacing, DMA, and Interrupts in 8085/8086

TAKEAWAYS:

• Memory-mapped I/O and isolated I/O differ in how devices are addressed (memory locations vs. dedicated ports).
• DMA bypasses the CPU for bulk data transfers, reducing CPU overhead (e.g., disk drives, network cards).
• Interrupts enable asynchronous event handling (vectored vs. non-vectored, priority-based).
• The 8237 DMAC and 8259 PIC are hardware components for DMA and interrupt management.
• Segment registers (CS, DS, SS, ES) in 8086 manage memory segmentation for efficient addressing.

Memory Interfacing: How the CPU Talks to Memory

The CPU communicates with memory using address buses, data buses, and control signals (MREQ, RD, WR). Memory can be accessed in two ways:

1. Memory-Mapped I/O: Devices share the same address space as memory (e.g., 8086 uses IN/OUT instructions for isolated I/O but memory-mapped for some peripherals).
2. Isolated I/O: Dedicated I/O ports (e.g., 8085 uses IN/OUT instructions with port addresses).

Real-world example: In eSewa, when you pay an electricity bill, the server processes your request via memory-mapped I/O to interact with databases and payment gateways. The CPU reads/writes data to/from memory locations where device registers (e.g., network cards) are mapped.

Direct Memory Access (DMA): Bypassing the CPU

DMA allows high-speed devices (e.g., hard drives, network cards) to transfer data directly to/from memory without CPU intervention. The 8237 DMAC (Direct Memory Access Controller) manages this.

How DMA Works

1. Device requests DMA via HRQ (Hold Request).
2. CPU grants HLDA (Hold Acknowledge) and releases buses.
3. DMAC transfers data in burst mode (e.g., 16-bit words).
4. CPU regains control after transfer completes.

sequenceDiagram
    Device->>DMAC: HRQ (Hold Request)
    DMAC->>CPU: HLDA (Hold Acknowledge)
    CPU-->>Device: Releases Buses
    DMAC->>Memory: Writes Data (DMA Cycle)
    Memory-->>Device: Acknowledges
    DMAC->>CPU: End of Transfer
    CPU->>DMAC: Resumes Control

Real-world example: When you upload a file on Daraz, the server uses DMA to transfer large data chunks from the network card to RAM without CPU delays, speeding up the process.

8237 DMAC Architecture

Key registers:

• Base Address Register: Starting memory location.
• Word Count Register: Number of bytes to transfer.
• Current Address Register: Tracks progress.

Timing Diagram for DMA Transfer:

Interrupts: Handling Asynchronous Events

Interrupts allow the CPU to respond to events (e.g., keyboard input, timer overflow) without polling. Two types:

1. Non-vectored: CPU executes a fixed interrupt service routine (ISR).
2. Vectored: CPU jumps to an address stored in an Interrupt Vector Table (e.g., 8085 uses RST instructions).

Interrupt Sources in 8085/8086

Real-world example: When you press a key in WhatsApp, the keyboard controller sends an interrupt to the CPU, which then processes the input without waiting for a loop check.

8259 PIC (Programmable Interrupt Controller)

Manages multiple interrupts with priority levels and cascading (chaining multiple PICs).

stateDiagram-v2
    [*] --> Idle
    Idle --> Pending : Interrupt Request (IRQ)
    Pending --> ISR : Acknowledge (INTA)
    ISR --> End : Service Complete
    End --> Idle : EOI (End of Interrupt)

Example: In Ncell’s billing system, the 8259 PIC prioritizes critical interrupts (e.g., network failure) over less urgent ones (e.g., SMS alerts).

Memory Segmentation in 8086

The 8086 uses segmented memory (1MB address space) with 4 segment registers:

• CS: Code Segment (for instructions).
• DS: Data Segment (for variables).
• SS: Stack Segment (for stack operations).
• ES: Extra Segment (for additional data).

Effective Address Calculation:

Physical Address = (Segment Register × 16) + Offset

Example: If DS = 1234H and Offset = 5678H, the physical address is:

12340H + 5678H = 179B8H

Real-world example: In NEPSE’s stock trading software, the 8086’s segmented memory helps manage large datasets (e.g., stock prices) by dividing them into logical segments (e.g., DS for current prices, ES for historical data).

I/O Instructions in 8085/8086

Worked Example: Calculate the sum of 10 bytes stored at 6000H (8085).

    MVI H, 60H    ; Load high byte of address
    MVI L, 00H    ; Load low byte of address
    MVI C, 0AH    ; Counter = 10
    MVI B, 00H    ; Sum register
LOOP: LHLD 6000H  ; Load 16-bit data
    ADD B         ; Add to sum
    MOV B, A      ; Store sum in B
    INX H         ; Increment address
    DCR C         ; Decrement counter
    JNZ LOOP      ; Repeat if not zero
    STA 6010H     ; Store final sum

DMA vs. Interrupt-Driven I/O

Real-world example: Pathao’s ride-hailing app uses interrupts for real-time GPS updates (low data) but DMA for bulk image transfers (e.g., driver photos).

Exam Tip

1. Draw diagrams: Always sketch the 8237 DMAC block diagram and 8259 PIC timing for interrupt handling.
2. Compare I/O methods: Memorize the differences between memory-mapped vs. isolated I/O and DMA vs. interrupt-driven I/O.
3. Segment registers: Know how CS, DS, SS, and ES work in 8086 (e.g., CS:IP for instruction pointer).
4. Worked examples: Practice writing 8085 assembly for array sums/averages using LHLD/SHLD.
5. Real-world links: Relate DMA to file uploads (Daraz) and interrupts to keyboard input (WhatsApp).