Explain Register Organization in 80386 microprocessor.

The 80386 is a 32-bit microprocessor. Its registers fall into these groups:

1. General-purpose registers (32-bit): EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP. The lower 16 bits can be used as AX, BX, CX, DX, SI, DI, BP, SP (as in the 8086), and AX, BX, CX, DX split further into AH/AL, BH/BL, CH/CL and DH/DL.

• EAX: accumulator. EBX: base. ECX: count (loops, shifts). EDX: data (multiply, divide, I/O).
• ESI and EDI: source and destination index for string operations.
• EBP: base pointer for the stack frame. ESP: stack pointer.

2. Segment registers (16-bit): CS (code), DS (data), SS (stack), ES, FS and GS (extra data segments; FS and GS are new in the 80386). In protected mode they hold selectors that point to segment descriptors.

3. Instruction pointer and flags:

• EIP (32-bit) holds the offset of the next instruction.
• EFLAGS (32-bit) holds the status flags (CF, PF, AF, ZF, SF, OF), the control flags (TF, IF, DF), and new flags such as IOPL, NT, RF (resume) and VM (virtual 8086 mode).

4. Control registers:

• CR0: mode control, including PE (protected mode enable) and PG (paging enable).
• CR2: the linear address that caused a page fault.
• CR3: the base address of the page directory.

5. System address registers: GDTR and IDTR hold the base and limit of the global descriptor table and interrupt descriptor table; LDTR and TR hold selectors for the local descriptor table and the task state segment.

6. Debug and test registers: DR0–DR7 for hardware breakpoints, and TR6–TR7 for testing the translation lookaside buffer (TLB).