Computer Architecture Basics: Components, Buses, ISA & Flynn’s Taxonomy

Core Concepts: What is Computer Architecture?

Computer architecture defines the structure, organization, and behavior of a computer system. It bridges the gap between hardware design (how components are built) and software execution (how programs run). Unlike computer organization (which focuses on gates, circuits, and timing), architecture deals with visible components (e.g., registers, ALU, memory) and their logical interactions.

Key Definitions

• Computer System: A collection of hardware and software components working together to process data.
• Computer Organization: How hardware components are interconnected (e.g., buses, caches).
• Computer Architecture: The logical design of components (e.g., instruction sets, register sizes).
• Instruction Set Architecture (ISA): The contract between hardware and software (e.g., x86, ARM). It defines:
  • Instruction formats (e.g., ADD R1, R2, R3).
  • Registers (e.g., PC, SP, IR).
  • Memory addressing modes.

1. Major Components of a Computer System

A computer consists of five primary components, each with a distinct role:

IMAGE: CPU and Motherboard Components

![CPU motherboard diagram with labeled parts](/media/33936583d128818b238b.jpg "A real motherboard showing CPU socket, RAM slots, chipset, and buses. (Image: Happie1Soul, CC BY-SA 4.0, via Wikimedia Commons)")

Why this matters: The CPU (e.g., Intel Core i7) is the "engine," while the motherboard connects all parts via buses.

2. System Bus: The Backbone of Communication

The system bus is a shared communication pathway between components. It consists of three sub-buses:

Types of Buses

graph LR
    A["System Bus"] --> B["Data Bus"]
    A --> C["Address Bus"]
    A --> D["Control Bus"]
    B -->|"Carries data between CPU, memory, I/O"| E[(CPU ↔ Memory ↔ I/O)]
    C -->|"Specifies memory location"| F[(CPU → Memory)]
    D -->|"Handshakes (e.g., READ/WRITE)"| G[(CPU ↔ Memory)]

• Data Bus: Bidirectional (8/16/32/64-bit width). Example: A 32-bit bus transfers 4 bytes (32 bits) at once.
• Address Bus: Unidirectional (CPU → Memory). Determines memory size:
  • 16-bit address bus → $2^{16}=64$ KB addressable memory.
  • 32-bit → $2^{32}=4$ GB.
• Control Bus: Carries signals like:
  • MEMREAD, MEMWRITE, IRQ (interrupt request), CLK (clock).

Worked Example: Bus Width and Data Transfer

Scenario: A computer has a 16-bit data bus and a 24-bit address bus. Calculate:

1. Maximum addressable memory.
2. Data transferred in one clock cycle.

Solution:

1. Addressable memory = $2^{24}=16$ MB.
2. Data per cycle = 16 bits = 2 bytes.

Real-World Tie-In:

• eSewa App (Nepal): When you pay a bill, the app sends data (e.g., transaction ID, amount) via the data bus to the server. The address bus locates the correct memory/register to store/update your payment record.

3. Instruction Set Architecture (ISA): The Hardware-Software Contract

ISA defines how a CPU interacts with software. It includes:

• Instruction Formats: How instructions are encoded (e.g., OPCODE, operands).
• Registers: Temporary storage (e.g., PC = Program Counter, IR = Instruction Register).
• Addressing Modes: How operands are specified (e.g., immediate, direct, indirect).

Instruction Format

An instruction typically has:

1. Opcode: Operation to perform (e.g., ADD, SUB).
2. Operands: Data/addresses (e.g., registers, memory locations).

Example (32-bit ISA):

0000 0010 0000 0001 0000 0010 0000 0011
|-------|-------|-------|-------|
Opcode  R1     R2     R3

• Opcode = 00000010 → ADD
• R1 = 00000001, R2 = 00000010, R3 = 00000011 → ADD R1, R2, R3

Instruction Cycle: FETCH-DECODE-EXECUTE

stateDiagram-v2
    [*] --> FETCH: PC → IR, PC++
    FETCH --> DECODE: IR → Control Unit
    DECODE --> EXECUTE: ALU/Registers
    EXECUTE --> [*]

Microoperations in FETCH Phase:

1. PC → MAR: Program Counter sends address to Memory Address Register.
2. MEMREAD: Control bus signals memory to send data.
3. MDR → IR: Memory Data Register loads instruction into Instruction Register.
4. PC++: Increment PC for next instruction.

Circuit Diagram (Simplified):

4. Flynn’s Classification: Types of Computer Architectures

Flynn classified computers based on instruction and data streams:

Real-World Examples of Flynn’s Taxonomy

1. Pathao (Nepal):
   • Uses MIMD architecture for its driver dispatch system. Multiple servers (instructions) process multiple ride requests (data streams) in parallel to optimize routes.
2. YouTube (Google):
   • SIMD in GPUs accelerates video encoding/decoding for millions of users simultaneously.
3. Nepal Stock Exchange (NEPSE):
   • SISD for traditional trading systems (single instruction processing trades sequentially).

5. CISC vs. RISC: Architectural Philosophies

Worked Example: CISC vs. RISC in a Bank Loan Calculator

Scenario: A bank’s software calculates monthly loan payments using the formula: $$\text{Monthly Payment}=P\times \frac{r(1+r{)}^n}{(1+r{)}^n-1}$$

• CISC Approach: A single LOAN_CALC P, r, n instruction handles everything in hardware.
• RISC Approach: Broken into steps:
  1. LOAD P
  2. LOAD r
  3. MUL r, (1 + r)
  4. POW n, (1 + r)
  5. ... (many simple steps).

Why RISC Wins Here:

• Faster compilation: Modern compilers optimize simple instructions better.
• Pipelining: RISC’s fixed-cycle instructions enable deeper pipelines (see Unit 6).

In the Real World

1. Khalti (Nepal):

   • Uses MIMD architecture for its payment processing servers. Multiple servers (instructions) handle multiple transactions (data streams) in parallel to prevent delays during festivals like Dashain/Tihar.
   • ISA Role: The servers use x86-64 (CISC) for compatibility but rely on RISC-like optimizations in their databases (e.g., PostgreSQL) for speed.

2. Daraz (Nepal):

   • SIMD in their recommendation engines: GPUs process multiple user preferences (data streams) simultaneously to suggest products faster than a single CPU could.

3. NTC (Nepal Telecom):

   • SISD for traditional billing systems, but MIMD for modern 5G network slicing, where different "slices" (e.g., voice, IoT) run on separate cores.

Exam Tip

1. Diagrams Are Key:

   • Always draw bus structures, instruction formats, and Flynn’s taxonomy tables in exams. Label every part!
   • For FETCH cycle, show PC → MAR → MDR → IR with arrows.

2. ISA vs. Organization:

   • ISA = What the programmer sees (e.g., ADD R1, R2).
   • Organization = How it’s built (e.g., hardwired vs. microprogrammed control, covered in Unit 4).

3. Common Pitfalls:

   • Mixing CISC/RISC: Remember RISC = fewer, simpler instructions; CISC = complex instructions.
   • Bus Width: $2^n$ addressable memory = $n$-bit address bus. Don’t forget powers of 2!
   • Flynn’s Types: MISD is rare; focus on SISD, SIMD, MIMD.

4. Short Notes:

   • For questions like "Explain the common bus system", describe data, address, and control buses with a Mermaid diagram and one example (e.g., "A 32-bit data bus transfers 4 bytes per cycle").

Summary Checklist

Before the exam, ensure you can: ✅ Define computer architecture vs. organization. ✅ Draw and label the three buses (data, address, control). ✅ Explain the FETCH cycle with microoperations. ✅ Compare CISC vs. RISC with examples. ✅ Classify Flynn’s four types and give two real-world examples for each. ✅ Calculate memory size from address bus width.