Computer Abstractions: Layers, Components & Real-World Systems

Why Abstraction Matters: The Layers of a Computer

Computers are complex systems, but abstraction lets us break them into manageable layers. Each layer hides details from the layer above, making design and debugging easier. The key layers are:

1. Hardware Hierarchy: From Gates to Systems

Computers are built from five fundamental abstraction levels:

1. Digital Logic (gates, flip-flops, registers)
2. Combinational/Sequential Circuits (ALUs, decoders, counters)
3. Microarchitecture (CPU, memory, I/O)
4. Operating System (process management, memory allocation)
5. Applications (user programs, APIs)

flowchart LR
    A["Digital Logic\n(Gates, Flip-flops)"] --> B["Combinational/Sequential\nCircuits\n(ALU, Registers)"]
    B --> C["Microarchitecture\n(CPU, Memory, Bus)"]
    C --> D["Operating System\n(Kernel, Drivers)"]
    D --> E["Applications\n(Software, Apps)"]
    E -->|"User"| F["Human Interface"]
    C -->|"Hardware"| G["Peripherals\n(Keyboard, Monitor)"]

The first 4-bit microprocessor (1971), showing how abstraction started with a single chip. (Image: Mister rf, CC BY-SA 4.0, via Wikimedia Commons)

The von Neumann Architecture: The Blueprint of Modern Computers

Most computers follow the von Neumann model, which defines:

• A central processing unit (CPU) (for arithmetic/logic)
• Memory (to store data/instructions)
• Input/Output (I/O) devices
• A bus system to connect them.

How It Works: The Fetch-Decode-Execute Cycle

1. Fetch: CPU gets the next instruction from memory via the address bus and data bus.
2. Decode: Instruction is split into opcode (operation) and operand (data).
3. Execute: CPU performs the operation (e.g., add, store).
4. Store: Result is written back to memory or an output device.

flowchart TD
    A["Memory\n(Instructions/Data)"] -->|"Address Bus"| B["CPU\n(ALU, CU, Registers)"]
    B -->|"Data Bus"| C["Memory"]
    B -->|"Control Bus"| D["I/O Devices\n(Keyboard, Monitor)"]
    B --> E["Fetch\nInstruction"]
    E --> F["Decode\nOpcode/Operand"]
    F --> G["Execute\nALU Operation"]
    G --> H["Store\nResult"]

Worked Example: Loading a Number into a Register Suppose we load the value 5 (binary 0101) from memory address 0x1000 into register R1:

1. Fetch: CPU sends 0x1000 via the address bus.
2. Decode: Instruction is LOAD R1, [0x1000].
3. Execute: CPU reads 0101 from memory via the data bus and stores it in R1.
4. Store: R1 now holds 5.

Bus Systems: The Nervous System of a Computer

Buses are shared communication pathways between components. There are three main types:

Performance Trade-offs in Bus Design

• Width: A 32-bit bus can transfer 4 bytes at once (faster than 8-bit).
• Speed: Clock speed (e.g., 3.5 GHz) determines how many cycles per second.
• Multiplexing: Some buses (e.g., address/data multiplexed) share lines to save space.

Real-World Example: eSewa’s Payment System When you pay a bill via eSewa:

1. Your phone sends a transaction request (data) over a bus-like network to eSewa’s server.
2. The server decodes the request (e.g., "Debit Rs. 500 from account X").
3. The database (memory) fetches your balance via the address bus (query).
4. The ALU (arithmetic logic unit) checks if funds are sufficient.
5. The result is sent back to your phone via the data bus.

Performance Metrics: How Fast Is Your Computer?

Key metrics to compare systems:

Worked Example: Calculating MIPS A CPU runs at 2.5 GHz with a CPI of 2.5.

• MIPS = $\frac{2.5\times 10^9}{2.5\times 10^6}=1000$ MIPS.

A labeled diagram of a system bus connecting CPU, RAM, and I/O. (Image: W Nowicki, CC BY-SA 3.0, via Wikimedia Commons)

Memory Hierarchy: Why Fast Memory Is Expensive

Computers use a memory hierarchy to balance speed, cost, and capacity:

How Caching Works: A Hit vs. Miss

• Cache Hit: Data is in cache → fast access (e.g., L1 cache hit = 0.5 ns).
• Cache Miss: Data must be fetched from slower memory → delay (e.g., L2 miss = 3 ns + RAM access).

Worked Example: Cache Hit Rate If a program has a 95% L1 cache hit rate and 5% miss rate (requiring L2 access):

• Average access time = $(0.95\times 0.5)+(0.05\times 3)=0.475+0.15=0.625$ ns.

Input/Output Systems: Connecting the Outside World

I/O devices (keyboard, monitor, network card) interact with the CPU via:

1. Programmed I/O: CPU polls devices (slow, wastes cycles).
2. Interrupt-Driven I/O: Device sends an interrupt when ready (faster).
3. DMA (Direct Memory Access): Device transfers data directly to memory without CPU help (used in high-speed transfers like video streaming).

Real-World Example: Pathao’s Ride-Hailing System

When you request a ride on Pathao:

1. Your phone sends a location update (I/O) to Pathao’s server.
2. The server’s CPU processes the request (fetch-decode-execute).
3. The database (memory) fetches nearby drivers (cache hit/miss).
4. A DMA controller might handle high-speed image uploads from the driver’s app.

In the Real World

1. eSewa (Nepal)

   • Idea Used: von Neumann architecture (CPU fetches instructions, memory stores transactions, I/O handles QR scans).
   • How: When you scan a QR code, your phone’s CPU decodes the transaction (fetch-decode-execute), while eSewa’s server validates it via database queries (memory access).

2. Ncell’s 4G Network

   • Idea Used: Bus systems & memory hierarchy.
   • How: Your phone’s data bus sends/receives signals to the 4G tower. The tower’s CPU processes your call (using L1/L2 cache for fast routing) before sending it to the destination.

3. Daraz’s Order Fulfillment

   • Idea Used: Interrupt-driven I/O & DMA.
   • How: When you place an order, Daraz’s server uses DMA to quickly transfer your order details to the warehouse system (instead of polling). An interrupt triggers when stock is low, alerting the inventory team.

Exam Tip

What to Expect in TU/PU Exams

1. Diagram-Based Questions (30%)

   • Draw and label:
     • von Neumann architecture.
     • Bus systems (data/address/control).
     • Memory hierarchy pyramid.
   • Common Mistake: Forgetting to label arrows (e.g., "data bus" vs. "address bus").

2. Calculations (25%)

   • MIPS, CPI, cache hit rates.
   • Example Question: "A CPU runs at 3 GHz with CPI=3. Calculate MIPS if it executes 10⁹ instructions." Solution: $\text{MIPS}=\frac{3\times 10^9}{3\times 10^6}=1000$ MIPS.

3. Short Answer (20%)

   • Define:
     • Abstraction layer.
     • Interrupt vs. Polling.
     • Why SRAM is faster than DRAM.
   • Example: "Why is L1 cache smaller than L3?" Answer: "L1 is SRAM (fast but expensive), while L3 is larger but slower SRAM or shared cache."

4. Scenario-Based (15%)

   • Example: "Explain how a bank’s ATM uses the von Neumann model to process a withdrawal." Key Points:
     • CPU fetches PIN check instruction.
     • Memory stores account balance.
     • I/O handles card reader and cash dispenser.

5. True/False (10%)

   • Example: "DMA reduces CPU overhead in I/O operations." Answer: True (DMA transfers data directly to memory).

How to Score Full Marks

✅ Draw diagrams neatly (label every bus, arrow, and component). ✅ Show calculations step-by-step (e.g., MIPS = Clock Rate / (CPI × 10⁶)). ✅ Relate to real systems (e.g., "Like eSewa’s transaction processing"). ✅ Use bullet points for comparisons (e.g., SRAM vs. DRAM table). ✅ Practice past papers (TU/PU often repeat questions on cache hit rates and bus types).