Arithmetic Circuits & Advanced Topics: Adders, Subtractors, ALUs, Multipliers, Dividers, PLA, ROM

TAKEAWAYS:

• Understand full adders/subtractors and their cascading for multi-bit arithmetic, with ripple-carry vs. carry-lookahead tradeoffs.
• Design arithmetic logic units (ALUs) combining logic and arithmetic operations for CPUs.
• Implement multipliers/dividers using shift-and-add/subtract methods and Wallace trees.
• Master PLA and ROM as programmable logic alternatives to hardwired gates.
• Apply BCD and Gray code conversions for real-world data encoding (e.g., sensors, displays).
• Optimize circuits using K-maps for minimal gate count (critical for exam questions).

1. Arithmetic Circuits: Adders and Subtractors

1.1 Full Adder and Ripple-Carry Adder

A full adder adds three inputs (two bits A, B and a carry-in C_in) and produces a sum (S) and carry-out (C_out). The truth table and logic equations are:

Logic Equations: $$S=A\oplus B\oplus C_{in},C_{out}=(A\cdot B)+(B\cdot C_{in})+(A\cdot C_{in})$$

Circuit Diagram: Ripple-Carry Adder: For N-bit addition, full adders are cascaded. The carry propagates from LSB to MSB, causing delay (critical for high-speed systems like CPUs).

Example: Design a 4-bit ripple-carry adder for adding A = 1011 and B = 0110. Solution:

• Use 4 full adders in series.
• Output: S = 0001, C_out = 1 (since 1011 + 0110 = 10001 in binary).

Real-World Use:

• Khalti’s payment processing uses ripple-carry adders in microcontrollers to verify transaction totals.
• Ncell’s billing system calculates data usage sums for monthly charges.

1.2 Full Subtractor and Ripple-Borrow Subtractor

A full subtractor subtracts B from A with a borrow-in (B_in) and produces a difference (D) and borrow-out (B_out).

Truth Table:

Logic Equations: $$D=A\oplus B\oplus B_{in},B_{out}=(A^{\prime }\cdot B)+(A^{\prime }\cdot B_{in})+(B\cdot B_{in})$$

Example: Subtract B = 0101 from A = 1010 using a 4-bit ripple-borrow subtractor. Solution:

• Output: D = 0101, B_out = 1 (since 1010 - 0101 = 0101 with borrow).

Real-World Use:

• eSewa’s refund calculations use subtractors to adjust balances.
• Bank loan interest computations rely on subtraction circuits in ATMs.

1.3 Carry-Lookahead Adder (CLA)

Problem with Ripple-Carry Adders:

• Delay increases linearly with bit-width (O(N)).
• Solution: Carry-Lookahead Adder (CLA) computes carries in parallel.

Key Idea:

• Generate (G_i) and Propagate (P_i) signals: $$G_i=A_i\cdot B_i,P_i=A_i\oplus B_i$$
• Carry-out (C_{i+1}): $$C_{i+1}=G_i+P_i\cdot C_i$$

Example: Design a 4-bit CLA. Solution:

Advantage:

• Faster than ripple-carry (critical for CPUs like Intel’s ALUs).

Real-World Use:

• Google’s Tensor Processing Units (TPUs) use CLAs for high-speed matrix additions in AI training.

2. Arithmetic Logic Unit (ALU)

An ALU combines logic operations (AND, OR, NOT) and arithmetic operations (ADD, SUB).

Block Diagram:

Operations:

Example: Design an ALU for ADD, SUB, and AND. Solution:

• Use full adders for ADD/SUB.
• Use AND gates for logic operations.
• Control signals select the operation.

Real-World Use:

• Pathao’s fare calculator uses ALUs to compute distances and prices dynamically.

3. Multipliers and Dividers

3.1 Binary Multiplier (Shift-and-Add)

Method:

1. Shift multiplicand left for each bit of multiplier.
2. Add if multiplier bit is 1.

Example: Multiply A = 1011 (11) by B = 0101 (5). Steps:

Final Product: 110010 (50 in decimal).

Circuit:

Real-World Use:

• NEPSE’s stock price calculations use multipliers for percentage changes.

3.2 Binary Divider (Shift-and-Subtract)

Method:

1. Shift dividend left.
2. Subtract divisor if dividend ≥ divisor.
3. Set quotient bit to 1 if subtraction occurs.

Example: Divide A = 110010 (50) by B = 0101 (5). Steps:

Final Quotient: 10010 (10), Remainder: 0.

Real-World Use:

• Bank loan EMI calculators use dividers to split payments.

4. Programmable Logic Arrays (PLA) and ROM

4.1 PLA (Programmable Logic Array)

A PLA combines AND and OR planes for flexible logic implementation.

Structure:

flowchart LR
    Inputs["Inputs"] --> ANDPlane["AND Plane"]
    ANDPlane --> ORPlane["OR Plane"]
    ORPlane --> Outputs["Outputs"]

Advantage:

• Reduces gate count compared to hardwired logic.
• Programmable for different functions.

Example: Implement F(A,B,C) = Σ(1,3,6,7) using PLA. Solution:

• AND terms: AB'C, ABC', ABC, AB'C' (minterms).
• OR terms: Combine in OR plane.

Real-World Use:

• Smart traffic lights use PLAs to prioritize routes dynamically.

4.2 ROM-Based Logic

ROM stores precomputed logic functions (like a lookup table).

Example: Design a 3-to-8 decoder using ROM. Solution:

• Address inputs: A,B,C.
• Outputs: D0 to D7 (active high for matching inputs).

Real-World Use:

• NTC’s telephone exchange uses ROM for call routing tables.

5. Code Converters (BCD to Gray, Excess-3 to Gray)

5.1 BCD to Gray Code Converter

BCD (8421): 0000 to 1001 (0-9). Gray Code: Adjacent numbers differ by 1 bit.

Conversion Rule: $$G_i=B_i\oplus B_{i+1}(\text{for }i=0\text{ to }3)$$

Example: Convert BCD = 0101 (5) to Gray. Solution:

• G3 = 0, G2 = 0, G1 = 1, G0 = 1 → 0111.

Circuit:

Real-World Use:

• Digital thermometers use Gray code to minimize errors in temperature readings.

6. Exam Tip

Key Focus Areas:

1. Design Questions:

   • Always draw the circuit (use standard gate symbols).
   • For adders/subtractors, show carry/borrow propagation.
   • For ALUs, label control signals clearly.

2. K-Map Simplification:

   • Group don’t-cares to minimize gates.
   • Example: For F(A,B,C,D) = Σ(3,4,5,7,9,13,14,15), group 110X and 111X.

3. State Machines:

   • Mealy vs. Moore: Mealy outputs depend on inputs; Moore depends only on state.
   • Example: Design a traffic light controller (use JK flip-flops).

4. Real-World Applications:

   • Banks: Use ALUs for transaction validation.
   • E-commerce (Daraz): Multipliers for bulk discounts.
   • Telecom (Ncell): Encoders/Decoders for signal modulation.

Common Mistakes to Avoid:

• Forgetting carry/borrow in adders/subtractors.
• Incorrect K-map grouping (e.g., overlapping groups).
• Missing don’t-care conditions in PLA/ROM design.

Final Note: Master adder/subtractor designs, ALU structures, and code conversions—these are high-weightage in exams. Practice timing diagrams for sequential circuits and K-maps for simplification. Good luck! 🚀