Combinational Logic Circuits: Design, Analysis & Applications

Key Concepts and Definitions

Combinational circuits are memoryless circuits where outputs are solely determined by current inputs. They are built using logic gates, multiplexers, decoders, and arithmetic circuits. Unlike sequential circuits, they do not store state (no flip-flops or registers).

1. Core Components

• Logic Gates: Basic building blocks (AND, OR, NOT, NAND, NOR, XOR, XNOR).
• Multiplexers (MUX): Select one of many inputs to send to a single output (used in data routing).
• Demultiplexers (DEMUX): Distribute a single input to multiple outputs (used in address decoding).
• Encoders: Convert multiple inputs into a coded output (e.g., priority encoders).
• Decoders: Convert coded inputs into multiple outputs (e.g., BCD to 7-segment decoders).
• Arithmetic Circuits: Perform operations like addition, subtraction, and comparison (e.g., full adders, subtractors).

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2. Designing Combinational Circuits

Step-by-Step Design Process

1. Problem Analysis: Define inputs, outputs, and logic requirements.
2. Truth Table: List all possible input combinations and corresponding outputs.
3. Boolean Expression: Derive the logic equation from the truth table.
4. Simplification: Use Karnaugh Maps (K-Maps) or Boolean algebra to minimize the expression.
5. Logic Diagram: Implement the simplified expression using gates or standard ICs (e.g., 74LS83 for adders).

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Example 1: 3-Bit Odd Parity Generator

Problem: Design a circuit that generates a parity bit (1 for odd number of 1s, 0 for even) for a 3-bit input. Solution:

1. Truth Table:

   | A | B | C | Parity (P) |
   |---|---|---|------------|
   | 0 | 0 | 0 |     0      |
   | 0 | 0 | 1 |     1      |
   | 0 | 1 | 0 |     1      |
   | 0 | 1 | 1 |     0      |
   | 1 | 0 | 0 |     1      |
   | 1 | 0 | 1 |     0      |
   | 1 | 1 | 0 |     0      |
   | 1 | 1 | 1 |     1      |
   

2. Boolean Expression: $P=\overline{A}\overline{B}C+\overline{A}B\overline{C}+A\overline{B}\overline{C}+ABC$
3. Simplified Expression (using K-Map): $P=A\oplus B\oplus C$ (XOR of all inputs).
4. Logic Diagram:

```figure
{"type":"circuit","inputs":["A","B","C"],"gates":[{"id":"xor1","type":"XOR","in":["A","B"],"out":["X1"]},{"id":"xor2","type":"XOR","in":["X1","C"],"out":["Parity"]}],"outputs":[{"name":"Parity","from":"xor2.out"}],"caption":"3-bit odd parity generator (XOR tree for A, B, C)."}

(A real image of a 3-input XOR gate IC like 74LS86 would appear here.)

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Example 2: Full Adder Using Half Adders

Problem: Design a full adder using two half adders and an OR gate. Solution:

1. Half Adder Truth Table:

   | A | B | Sum | Carry |
   |---|---|-----|-------|
   | 0 | 0 |  0  |   0   |
   | 0 | 1 |  1  |   0   |
   | 1 | 0 |  1  |   0   |
   | 1 | 1 |  0  |   1   |
   

2. Full Adder Logic:
   • Use two half adders:
     • First half adder adds ( A ) and ( B ), producing ( S_1 ) (sum) and ( C_1 ) (carry).
     • Second half adder adds ( S_1 ) and ( C_{in} ), producing ( Sum ).
     • The final carry ( C_{out} = C_1 + (S_1 \cdot C_{in}) ).
3. Logic Diagram:

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3. Code Converters

Example 3: Excess-3 to Gray Code Converter

Problem: Convert a 4-bit Excess-3 code to Gray code. Solution:

1. Excess-3 to BCD: Subtract 3 from the input (since Excess-3 is BCD + 3).
2. BCD to Gray Code: Use the standard conversion formula: ( G_1 = B_1 ) ( G_2 = B_1 \oplus B_2 ) ( G_3 = B_2 \oplus B_3 ) ( G_4 = B_3 \oplus B_4 )
3. Logic Diagram: (A 4-bit Gray code converter circuit would be drawn here, showing XOR gates for each bit.)

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4. Multiplexers and Demultiplexers

Multiplexer (MUX)

• Function: Selects one of ( 2^n ) inputs to send to a single output based on ( n ) select lines.
• Example: 4-to-1 MUX truth table:

  | S1 | S0 | I0 | I1 | I2 | I3 | Y |
  |----|----|----|----|----|----|---|
  | 0  | 0  | 0  | 1  | 0  | 1  | I0|
  | 0  | 1  | 0  | 1  | 0  | 1  | I1|
  | 1  | 0  | 0  | 1  | 0  | 1  | I2|
  | 1  | 1  | 0  | 1  | 0  | 1  | I3|
  

• Application: Used in data routing (e.g., selecting between multiple sensors in an IoT device).

Demultiplexer (DEMUX)

• Function: Routes a single input to one of ( 2^n ) outputs based on select lines.
• Example: 1-to-4 DEMUX truth table:

  | S1 | S0 | Y0 | Y1 | Y2 | Y3 |
  |----|----|----|----|----|----|
  | 0  | 0  | I  | 0  | 0  | 0  |
  | 0  | 1  | 0  | I  | 0  | 0  |
  | 1  | 0  | 0  | 0  | I  | 0  |
  | 1  | 1  | 0  | 0  | 0  | I  |
  

• Application: Used in memory addressing (e.g., selecting a specific RAM location).

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5. Arithmetic Circuits

Full Adder and Subtractor

• Full Adder:
  • Adds two bits and a carry-in, producing a sum and carry-out.
  • Truth table:

    | A | B | C_in | Sum | C_out |
    |---|---|------|-----|-------|
    | 0 | 0 |  0   |  0  |   0   |
    | 0 | 0 |  1   |  1  |   0   |
    | 0 | 1 |  0   |  1  |   0   |
    | 0 | 1 |  1   |  0  |   1   |
    | 1 | 0 |  0   |  1  |   0   |
    | 1 | 0 |  1   |  0  |   1   |
    | 1 | 1 |  0   |  0  |   1   |
    | 1 | 1 |  1   |  1  |   1   |
    

• Full Subtractor:
  • Subtracts two bits and a borrow-in, producing a difference and borrow-out.
  • Truth table:

    | A | B | Borrow_in | Diff | Borrow_out |
    |---|---|-----------|------|------------|
    | 0 | 0 |     0     |  0   |      0     |
    | 0 | 0 |     1     |  1   |      1     |
    | 0 | 1 |     0     |  1   |      1     |
    | 0 | 1 |     1     |  0   |      0     |
    | 1 | 0 |     0     |  1   |      0     |
    | 1 | 0 |     1     |  0   |      0     |
    | 1 | 1 |     0     |  0   |      0     |
    | 1 | 1 |     1     |  1   |      1     |
    

• Logic Diagram:

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6. Real-World Applications

In the Real World

1. eSewa Transaction Validation:

   • Uses parity generators to detect errors in financial transactions. If the parity bit doesn’t match, the transaction is flagged for review.
   • Example: A 3-bit parity generator ensures that payment data (e.g., amount, user ID) is transmitted correctly.

2. Daraz Order Prioritization:

   • Multiplexers route customer orders to different processing units based on priority (e.g., high-value orders go to faster servers).
   • Example: A 4-to-1 MUX selects between 4 order queues (standard, express, VIP, bulk) based on a 2-bit priority code.

3. Ncell Bill Calculation:

   • Full adders are used in hardware to sum up call durations, data usage, and SMS counts for billing.
   • Example: A 4-bit ripple-carry adder adds up minutes used in a month to compute the total call time.

4. Bank Loan Interest Calculation:

   • Arithmetic circuits (like subtractors) compute monthly installments by subtracting principal portions from loan amounts.
   • Example: A 16-bit subtractor deducts the principal repayment from the remaining loan balance.

5. Khalti Digital Payments:

   • Encoders convert user inputs (e.g., phone number, amount) into a compact code for secure transmission.
   • Example: A 4-to-2 priority encoder compresses the selected payment method (phone, card, bank) into a 2-bit code.

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7. Comparison Tables

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8. Advantages and Disadvantages

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Exam Tip

1. Design Questions:

   • Always start with a truth table. If the problem involves arithmetic (e.g., adder, subtractor), include a carry/borrow column.
   • For code converters, show the step-by-step conversion (e.g., Excess-3 to BCD to Gray).
   • Use K-Maps for simplification if the Boolean function has 4 or more variables. Show grouping clearly (highlight adjacent 1s and don’t-cares).

2. Circuit Realization:

   • Draw the logic diagram using standard gate symbols. Label all inputs, outputs, and intermediate signals.
   • For multiplexers/decoders, specify the select lines and enable pins if applicable.

3. Common Pitfalls:

   • Forgetting to account for don’t-care conditions in K-Maps (they can simplify the circuit further).
   • Misplacing carry/borrow propagation in ripple-carry adders/subtractors.
   • Not verifying the output for all input combinations (always check edge cases like all 0s or all 1s).

4. Short-Answer Questions:

   • For difference between encoder/decoder, emphasize:
     • Encoder: Many inputs → few outputs (compression).
     • Decoder: Few inputs → many outputs (expansion).
   • For De Morgan’s laws, prove them graphically (using NAND/NOR gates) and algebraically.

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9. Worked Example: BCD to Decimal Converter

Problem: Design a BCD to decimal converter using a 3-to-8 decoder. Solution:

1. BCD to Decimal Mapping:

   BCD | Decimal Outputs (D3 D2 D1 D0)
   0000 | 1 0 0 0 (0)
   0001 | 0 1 0 0 (1)
   0010 | 0 0 1 0 (2)
   0011 | 0 0 0 1 (3)
   0100 | 0 0 1 1 (4)
   0101 | 0 1 0 1 (5)
   0110 | 0 1 1 0 (6)
   0111 | 1 0 0 1 (7)
   1000 | 1 0 1 0 (8)
   1001 | 1 1 0 0 (9)
   

2. Logic:
   • Use a 3-to-8 decoder (74LS138) with BCD inputs ( B_2 B_1 B_0 ).
   • Enable the decoder only for valid BCD inputs (0000 to 1001). Invalid inputs (1010–1111) should output 0.
   • Enable Logic: ( \overline{E} = \overline{B_2 \cdot B_1 \cdot B_0} ) (disable for invalid BCD).
3. Circuit:

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10. Summary Checklist

Before attempting an exam question on combinational circuits, ensure you:

1. Have written a complete truth table (all input combinations).
2. Derived the Boolean expression correctly.
3. Simplified the expression using K-Maps or Boolean algebra.
4. Drawn the logic diagram with proper gate symbols and labels.
5. Verified the circuit with test cases (e.g., all 0s, all 1s, mixed inputs).
6. Included real-world relevance (e.g., how the circuit is used in eSewa/Khalti).

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(A photo of the actual 74LS83 IC would appear here, showing the pinout and package.)

(A photo of the 74LS151 IC would appear here.)