FETs: Types, Working, Biasing & Applications

Key Concepts & Structure

Field Effect Transistors (FETs) are voltage-controlled devices where the input current is negligible (unlike BJTs). They are classified into:

1. Junction Field Effect Transistor (JFET)
2. Metal-Oxide-Semiconductor FET (MOSFET)
   • Enhancement-mode MOSFET
   • Depletion-mode MOSFET

We will explore:

• Construction & working principle (channel formation, pinch-off)
• Characteristics curves (drain, transfer)
• Biasing techniques (self-bias, voltage-divider bias)
• Small-signal models (hybrid-π equivalent)
• Applications (amplifiers, switches, memory cells)
• Comparison with BJTs

1. Construction & Working Principle

1.1 JFET Structure

A JFET has:

• A semiconductor channel (N-channel or P-channel)
• A gate (P-type for N-channel JFET, N-type for P-channel JFET)
• Source (S) and Drain (D) terminals

graph LR
    A["N-channel JFET"] --> B["N-type Semiconductor Channel"]
    A --> C["P-type Gate"]
    B --> D["Source (S)"]
    B --> E["Drain (D)"]
    C -->|"Reverse-biased"| F["Depletion Region"]
    F -->|"Pinches off channel"| G["Current Flow"]

How it works:

• A reverse bias is applied to the gate, creating a depletion region that narrows the channel.
• As gate voltage $V_{GS}$ becomes more negative (for N-channel), the channel pinches off at $V_{GS}=V_P$ (pinch-off voltage).
• Drain current $I_D$ is controlled by $V_{GS}$, not $V_{GS}$.

N-channel JFET showing gate, source, drain, and depletion region. (Image: Vector version: VectorVoyager PNG version: Rparle at English, CC BY-SA 3.0, via Wikimedia Commons)

1.2 MOSFET Structure

MOSFETs have an insulated gate (SiO₂ layer), making them input-current-free and ideal for digital circuits.

graph LR
    A["N-channel Enhancement MOSFET"] --> B["N-type Substrate"]
    A --> C["P-type Well"]
    A --> D["SiO2 Insulator"]
    A --> E["Gate (Metal/Aluminum)"]
    C --> F["Source (S) & Drain (D)"]
    E -->|"Positive V_GS"| G["Inversion Layer"]
    G -->|"Forms channel"| H["Current Flow"]

Types of MOSFETs:

2. Characteristics Curves

2.1 Drain Characteristics ($I_D$ vs $V_{DS}$)

For a fixed $V_{GS}$:

• Cutoff region: $V_{DS}<V_{GS}-V_P$ (channel not pinched)
• Triode (ohmic) region: $V_{DS}$ increases, $I_D$ increases linearly
• Saturation (active) region: Channel pinches off; $I_D$ saturates

2.2 Transfer Characteristics ($I_D$ vs $V_{GS}$)

• For JFET: $$I_D=I_{DSS}{\left(1-\frac{V_{GS}}{V_P}\right)}^2\text{(for }{V}_{GS}\le V_P\text{)}$$ where:

  • $I_{DSS}$ = Drain current at $V_{GS}=0$
  • $V_P$ = Pinch-off voltage

• For Enhancement MOSFET: $$I_D=K_n(V_{GS}-V_{TH}{)}^2\text{(for }{V}_{GS}>V_{TH}\text{)}$$ where $K_n$ is the process transconductance parameter.

3. Biasing Techniques

Proper biasing ensures the FET operates in the active region for linear amplification.

3.1 Self-Bias (Most Common for JFET)

• Uses a source resistor $R_S$ to set $V_{GS}$.
• Advantages: Simple, stable against temperature variations.
• Disadvantage: Lower gain due to $R_S$.

Circuit:

graph LR
    A["V_DD"] --> B["Drain"]
    B --> C["R_D"]
    C --> D["Drain Terminal"]
    D --> E["Load"]
    D --> F["Ground"]
    G["Source"] --> H["R_S"]
    H --> I["Ground"]
    J["Gate"] --> K["Ground via R_G (optional)"]

Worked Example (Self-Bias for JFET): Given:

• $V_{DD}=20V$, $R_D=2k\Omega$, $R_S=1k\Omega$
• $I_{DSS}=8mA$, $V_P=-4V$

Find $V_{GS}$ and $I_D$:

1. Assume $I_D\approx I_{DSS}$ initially.
2. $V_{GS}=-I_D{R}_S$.
3. Use transfer characteristic equation: $$I_D=I_{DSS}{\left(1-\frac{V_{GS}}{V_P}\right)}^2$$
4. Solve iteratively (or use graph) to find $I_D=4mA$, $V_{GS}=-2V$.

Real-World Tie-In: In NTC’s power amplifiers, JFETs are self-biased to ensure stable operation across varying loads (e.g., speakers).

3.2 Voltage-Divider Bias (MOSFET)

• Uses a resistor network to set $V_{GS}$.
• Advantage: More stable than self-bias for MOSFETs.

Circuit:

graph LR
    A["V_DD"] --> B["R1"]
    B --> C["Gate"]
    C --> D["R2"]
    D --> E["Ground"]
    F["Drain"] --> G["R_D"]
    G --> H["Ground"]
    I["Source"] --> J["R_S"]
    J --> K["Ground"]

Worked Example (Voltage-Divider Bias for MOSFET): Given:

• $V_{DD}=15V$, $R_1=1M\Omega$, $R_2=500k\Omega$
• $V_{TH}=2V$, $K_n=2mA/V^2$

Find $V_{GS}$ and $I_D$:

1. $V_{GS}=V_{DD}\frac{R_2}{R_1+R_2}=15\times \frac{500k}{1.5M}=5V$
2. $I_D=K_n(V_{GS}-V_{TH}{)}^2=2mA/V^2\times (5-2{)}^2=18mA$

Real-World Tie-In: Khalti’s payment processing circuits use MOSFETs in voltage-divider bias to ensure stable gate voltages for high-speed switching in payment gateways.

4. Small-Signal Model (Hybrid-π Equivalent)

For AC analysis, FETs are modeled as:

• JFET/MOSFET:
  • Transconductance $g_m=\frac{\partial I_D}{\partial V_{GS}}$
  • Output resistance $r_o=\frac{V_A}{I_D}$ (Early effect)
  • Gate-source capacitance $C_{gs}$

Small-Signal Model:

graph LR
    A["V_gs"] --> B["g_m"]
    B --> C["I_d"]
    D["V_ds"] --> E["r_o"]
    E --> C
    F["C_gs"] -->|"Capacitor"| G["Gate to Source"]
    H["C_ds"] -->|"Capacitor"| I["Drain to Source"]

Calculating $g_m$: For JFET: $$g_m=\frac{2I_{DSS}}{|V_P|}\sqrt{1-\frac{V_{GS}}{V_P}}$$ For MOSFET (enhancement): $$g_m=2\sqrt{K_n{I}_D}$$

Worked Example: Given $I_{DSS}=8mA$, $V_P=-4V$, $V_{GS}=-2V$: $$g_m=\frac{2\times 8mA}{4V}\sqrt{1-\frac{-2}{-4}}=4mA/V\times \sqrt{0.5}=2.83mA/V$$

5. Applications of FETs

6. Comparison: FET vs BJT

7. Common Mistakes & Exam Tips

Mistakes to Avoid:

1. Confusing $V_P$ (JFET) and $V_{TH}$ (MOSFET):
   • $V_P$ is for JFET (pinch-off voltage).
   • $V_{TH}$ is for MOSFET (threshold voltage).
2. Ignoring the saturation region in biasing calculations.
3. Assuming MOSFETs work like JFETs (e.g., depletion vs enhancement modes).
4. Forgetting the Early effect ($r_o$) in small-signal models.

Exam Tips:

• Always check the region of operation (cutoff, triode, saturation).
• Memorize the transfer characteristic equations for JFET and MOSFET.
• Practice biasing circuits—examiners love numerical problems!
• Compare FET and BJT in terms of input impedance, noise, and applications.
• For MOSFETs, distinguish between enhancement and depletion modes.

Real Exam Question Example: "A JFET has $I_{DSS}=10mA$ and $V_P=-5V$. If $V_{GS}=-2V$, find $I_D$ and the small-signal transconductance $g_m$." Solution:

1. Use $I_D=I_{DSS}(1-V_{GS}/V_P{)}^2=10mA(1-(-2)/(-5){)}^2=3.6mA$.
2. $g_m=\frac{2I_{DSS}}{|V_P|}\sqrt{1-V_{GS}/V_P}=4mA/V\times \sqrt{0.6}=3.1mA/V$.

In the Real World

1. Ncell’s Base Stations

   • What? RF amplifiers use MOSFETs (e.g., GaN HEMTs) for high-frequency signal boosting.
   • Why FET? High efficiency, low distortion, and ability to handle high power at microwave frequencies.

2. eSewa’s Payment Processing

   • What? MOSFETs in switching regulators (e.g., buck converters) for efficient power conversion.
   • Why FET? Fast switching reduces power loss; enhancement-mode MOSFETs are used for digital control signals.

3. Daraz’s Warehouse Automation

   • What? JFET-based sensors detect inventory levels (e.g., load cells with JFET amplifiers).
   • Why FET? High input impedance prevents loading effects on sensitive sensors.

4. NTC’s Traffic Light Controllers

   • What? CMOS logic (FETs) controls timing sequences.
   • Why FET? Low power consumption and noise immunity in outdoor environments.

5. Khalti’s Security Chips

   • What? MOSFET-based EEPROM stores encryption keys.
   • Why FET? Non-volatile memory with high density and low power.

Summary Table for Quick Revision

Final Note: FETs are ubiquitous in modern electronics due to their efficiency, speed, and scalability. Master biasing, small-signal models, and comparisons with BJTs—these are high-weightage topics in exams. Always draw the circuit before solving numerical problems!